1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD209-3CAUGUST 2015JEDECSTANDARDLow Power Double Data Rate 3(LPDDR3)(Revision of JESD209-3B, August 2013)NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and sub
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7、information.Published byJEDEC Solid State Technology Association 20153103 North 10th StreetSuite 240 SouthArlington, VA 22201-2107This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or
8、resell the resulting material.PRICE: Contact JEDECPrinted in the U.S.A. All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by JEDEC and may not bereproduced without permission.For information, contact:JEDEC Solid State Technology Association3103 North 10th StreetSuite 240 Sout
9、hArlington, VA 22201-2107or refer to www.jedec.org under Standards-Documents/Copyright Information.JEDEC Standard No. 209-3CContents1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10、 Package ballout DQS1_t and DQS1_c to the data on DQ8 - DQ15.For x32 DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and DQS1_c to the data on DQ8 - DQ15, DQS2_t and DQS2_c to the data on DQ16 - DQ23, DQS3_t and DQS3_c to the data on DQ24 - DQ31.DM0-DM1 (x16) DM0 - DM3 (x32)Input Input
11、 Data Mask: DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS_t. Although DM is for input only, the DM loading shall match the DQ and DQS_t (or DQS_c). For x16 and x32 dev
12、ices, DM0 is the input data mask signal for the data on DQ0-7. DM1 is the input data mask signal for the data on DQ8-15.For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask signal for the data on DQ24-31.ODT Input On-Die Termination: This signal e
13、nables and disables termination on the DRAM DQ bus according to the specified mode register settings.VDD1Supply Core Power Supply 1: Core power supplyVDD2Supply Core Power Supply 2: Core power supply VDDCASupply Input Receiver Power Supply: Power supply for CA0-9, CKE, CS_n, CK_t, and CK_c input buf
14、fers.VDDQSupply I/O Power Supply: Power supply for data input/output buffers. VREF(CA)Supply Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all CA0-9, CKE, CS_n, CK_t, and CK_c input buffers.VREF(DQ)Supply Reference Voltage for DQ Input Receiver: Reference voltage
15、 for all data input buffers.VSSSupply GroundVSSCASupply Ground for Input ReceiversVSSQSupply I/O Ground: Ground for data input/output buffersZQ I/O Reference Pin for Output Drive Strength CalibrationPad Definition and DescriptionNOTE 1 Data includes DQ and DM.JEDEC Standard No. 209-3CPage 163 LPDDR3
16、 Functional DescriptionLPDDR3-SDRAM is a high-speed synchronous DRAM device internally configured as an 8-bank memory.These devices contain the following number of bits:1 Gb has 1,073,741,824 bits 2 Gb has 2,147,483,648 bits 4 Gb has 4,294,967,296 bits 6 Gb has 6,442,450,944 bits 8 Gb has 8,589,934,
17、592 bits 16 Gb has 17,179,869,184 bits 32 Gb has 34,359,738,368 bitsLPDDR3 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and bank information. Each command uses one clock cycl
18、e, during which command information is transferred on both the positive and negative edge of the clock.These devices also use a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially an 8n prefetch architecture with an interface
19、 designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR3 SDRAM effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half-clock-cycle data transfe
20、rs at the I/O pins.Read and write accesses to the LPDDR3 SDRAMs are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Activate command, which is then followed by a Read or Write
21、 command. The address and BA bits registered coincident with the Activate command are used to select the row and the bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access.Prior to n
22、ormal operation, the LPDDR3 SDRAM must be initialized. The following section provides detailed infor-mation covering device initialization, register definition, command description and device operation.3.1 LPDDR3 SDRAM AddressingTable 3 LPDDR3 SDRAM AddressingItems 1Gb 2Gb 4Gb 6Gb 8Gb 12Gb 16Gb 32Gb
23、Number of Banks 8 8 8 8 8 8 8 TBDBank Addresses BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 TBDtREFI(us)27.8 3.9 3.9 3.9 3.9 3.9 3.9 TBDx16Row Addresses R0-R12 R0-R13 R0-R13R0-R144R0-R14R0-R144R0-R14 TBDColumn Addresses1C0-C9 C0-C9 C0-C10 C0-C10 C0-C10 C0-C11 C0-C11 TBDx32Row Addresses R
24、0-R12 R0-R13 R0-R13R0-R144R0-R14R0-R144R0-R14 TBDColumn Addresses1C0-C8 C0-C8 C0-C9 C0-C9 C0-C9 C0-C10 C0-C10 TBDNOTE 1 The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero.NOTE 2 tREFIvalue for all bank refresh is for Tc = -2585 C, Tc means Operating C
25、ase Temperature. Depending on MR4 settings a refresh multiplier RM applies to the actually required refresh interval tREFIM= RM x tREFINOTE 3 Row and Column Address values on the CA bus that are not used are “dont care.”NOTE 4 No memory present at addresses with R13=R14=HIGH. ACT command with R13=R1
26、4=HIGH is ignored (NOP). Write to R13=R14=HIGH is ignored (NOP).JEDEC Standard No. 209-3CPage 173.2 Simplified LPDDR3 State DiagramLPDDR3-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related commands to control them. For a complete definition of the dev
27、ice behavior, the information provided by the state diagram should be integrated with the truth tables and timing specification. The truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of
28、 all the banks.For the command definition, see Clause 4, LPDDR3 Command Definitions and Timing Diagrams.SelfIdle1ReadingPrechargingWritingACTRDSREFREFPDMRRPDXPDXPDWRAutomatic SequenceCommand SequenceRDAWRARefreshingRefreshingPowerDownActivewith ReadingwithActiveReadingWritingPR(A) = Precharge (All)M
29、RW = Mode Register WriteSREF = Enter Self RefreshREF = RefreshPD = Enter Power DownPDX = Exit Power DownACT = ActivateWR(A) = Write (with Autoprecharge)RD(A) = Read (with Autoprecharge)SREFXMRAutoprechargeAutoprechargeDeepPower DPDXPowerDownOnMRR = Mode Register ReadSREFX = Exit Self RefreshDPD = En
30、ter Deep Power DownDPDX = Exit Deep Power Down MRRMRWDPDPowerAppliedMRWriting2MRReadingResettingMRReadingResetReset = Reset is achieved through MRW commandMRRRDA3WRA3ResetResettingActiveDownPowerIdleIdleFigure 1 LPDDR3: Simplified Bus Interface State DiagramPR, PRAPowerDownResettingPDPDXPR, PRARD3WR
31、3JEDEC Standard No. 209-3CPage 183.2 Simplified LPDDR3 State Diagram (contd)NOTE 1 In the Idle state, all banks are precharged.NOTE 2 In the case of MRW to enter CA Training mode or Write Leveling Mode, the state machine will not automatically return to the Idle state. In these cases an additional M
32、RW command is required to exit either operating mode and return to the Idle state. See sections “CA Training” or “Write Leveling”.NOTE 3 Terminated bursts are not allowed. For these state transitions, the burst operation must be completed before the transition can occur.NOTE 4 Use caution with this
33、diagram. It is intended to provide a floorplan of the possible state transitions and commands to control them, not all details. In particular, situations involving more than one bank are not captured in full detail.JEDEC Standard No. 209-3CPage 193.3 Power-up, Initialization, and Power-off 3.3.1 Vol
34、tage Ramp and Device InitializationThe following sequence must be used to power up the device. Unless specified otherwise, this procedure is mandatory.1. Voltage Ramp: While applying power (after Ta), CKE must be held LOW ( 0.2 VDDCA) and all other inputs must be between VILminand VIHmax. The device
35、 outputs remain at High-Z while CKE is held LOW.Following the completion of the voltage ramp (Tb), CKE must be maintained LOW. DQ, DM, DQS_t and DQS_c voltage levels must be between VSSQand VDDQduring voltage ramp to avoid latchup. CK_t, CK_c, CS_n, and CA input levels must be between VSSCAand VDDCA
36、during voltage ramp to avoid latch-up. Voltage ramp power supply requirements are provided in Table 4.Table 4 Voltage Ramp ConditionsNOTE 1 Ta is the point when any power supply first reaches 300 mV.NOTE 2 Noted conditions apply between Ta and power-off (controlled or uncontrolled).NOTE 3 Tb is the
37、point at which all supply and reference voltages are within their defined operating ranges.NOTE 4 Power ramp duration tINIT0(Tb - Ta) must not exceed 20 ms.NOTE 5 The voltage difference between any of VSS, VSSQ, and VSSCApins must not exceed 100 mV.Beginning at Tb, CKE must remain LOW for at least t
38、INIT1, after which CKE can be asserted HIGH. The clock must be stable at least tINIT2prior to the first CKE LOW-to-HIGH transition (Tc). CKE, CS_n, and CA inputs must observe setup and hold requirements (tIS, tIH) with respect to the first rising clock edge (as well as to subsequent falling and risi
39、ng edges).If any MRR commands are issued, the clock period must be within the range defined for tCKb. MRW commands can be issued at normal clock frequencies as long as all AC timings are met. Some AC parameters (for example, tDQSCK) could have relaxed timings (such as tDQSCKb) before the system is a
40、ppropriately configured. While keeping CKE HIGH, NOP commands must be issued for at least tINIT3(Td). The ODT input signal may be in undefined state until tISbefore CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal shall be statically held at either LOW or HIGH. The ODT input
41、 signal remains static until the power up initialization sequence is finished, including the expiration of tZQINIT.2. RESET Command: After tINIT3is satisfied, the MRW RESET command must be issued (Td). An optional PRECHARGE ALL command can be issued prior to the MRW RESET command. Wait at least tINI
42、T4while keeping CKE asserted and issuing NOP commands. Only NOP commands are allowed during time tINIT4.3. MRRs and Device Auto Initialization (DAI) Polling: After tINIT4is satisfied (Te), only MRR commands and power-down entry/exit commands are supported. After Te, CKE can go LOW in alignment with
43、power-down entry and exit specifications. MRR commands are only valid at this time if the CA bus does not need to be trained. CA Training may only begin after time Tf. User may issue MRR command to poll the DAI bit which will indicate if device auto initialization is complete; once DAI bit indicates
44、 completion, SDRAM is in idle state. Device will also be in idle state after tINIT5(max) has expired (whether or not DAI bit has been read by MRR command).As the memory output buffers are not properly configured by Te, some AC parameters must have relaxed timings before the system is appropriately c
45、onfigured.After the DAI bit (MR0, DAI) is set to zero by the memory device (DAI complete), the device is in the idle state (Tf). DAI status can be determined by issuing the MRR command to MR0. The device sets the DAI bit no later than tINIT5after the RESET command. The controller must wait at least
46、tINIT5(max) or until the DAI bit is set before proceeding.After. Applicable ConditionsTa is reached VDD1must be greater than VDD2200 mVVDD1and VDD2must be greater than VDDCA200 mVVDD1and VDD2must be greater than VDDQ200 mVVRefmust always be less than all other supply voltagesJEDEC Standard No. 209-3
47、CPage 203.3.1 Voltage Ramp and Device Initialization (contd)4. ZQ Calibration: If CA Training is not required, the MRW initialization calibration (ZQ_CAL) command can be issued to the memory (MR10) after time Tf. If CA Training is required, the CA Training may begin at time Tf. See “Mode Register Wr
48、ite - CA Training Mode” on page 66 for the CA Training command. No other CA commands (other than RESET or NOP) may be issued prior to the completion of CA Training. At the completion of CA Training (Tf), the MRW initialization calibration (ZQ_CAL) command can be issued to the memory (MR10).This comm
49、and is used to calibrate output impedance over process, voltage, and temperature. In systems where more than one LPDDR3 device exists on the same bus, the controller must not overlap MRW ZQ_CAL commands. The device is ready for normal operation after tZQINIT.5. Normal Operation: After tZQINIT(Tg), MRW commands must be used to properly configure the memory (for example the output buffer drive strength, latencies, etc.). Specifically, MR1, MR2, and MR3 must be set to configure the memory for the target frequency and memory configuration.After the initialization seque
