1、JEDEC STANDARD Test Methods to Characterize Voiding in Pre-SMT Ball Grid Array Packages JESD217.01 (Minor revision of JESD217, September 2010) OCTOBER 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved
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9、C Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 217.01 -i- Introduction As ball grid array component pitch continues to decrease, the need to characteriz
10、e solder voiding has become more significant. Solder void manifestation (type and/or sizes) has been used to determine process capability as a means of quality assurance during process transfer, and as indicators of process stability from in-line manufacturing monitors. This document describes how t
11、o characterize voids in solder spheres in ball grid array packages prior to surface-mount (SMT) reflow soldering. JEDEC Standard No. 217.01 -ii- JEDEC Standard No. 217.01 Page 1 TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES (From Board Ballot JCB-10-56, and JCB-16-18 formu
12、lated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and pr
13、escribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Test methods can be applied to several types of ball grid array packages such as FCBGA, PBGA, CBGA, and CCGA with minimum 0.5 mm ball-to-ball pitch and constructed with leaded and lead-free solder alloy
14、s. Guidelines for pre-SMT voids may not be sufficiently robust where ball grid array packages balls are assembled onto unfilled micro-via structures on package substrate land. Hence, the un-filled microvia construction (Figure 1-1a) is considered out-of-scope for this document, while filled via (Fig
15、ure 1-1b) is within scope. Figure 1-1 Illustration of Un-filled Microvia (1-1a) out-of-scope vs. Filled Microvia (1-1b) in-scope of document JEDEC Standard No. 217 Page 2 2 Terms and definitions ball grid array (BGA) packages: A package in which the external connections to the package are made via a
16、 rectangular array of ball-type connections, all on a common plane. (Ref. definition per JESD22-B112.) CBGA: Ceramic ball grid array package. CCGA: Ceramic column grid array package. field of view: The area of the test sample under metrology examination. flip chip ball grid array (FCBGA) package: A
17、type of ball grid array (BGA) package which consists of facedown die (flip chip FC) on organic substrate of package. NOTE FCBGA packages typically have a filled epoxy which is dispensed between the die and the substrate. leaded solder: A solder sphere composed primarily of tin (Sn) and lead (Pb) ele
18、ments. NOTE 67%/37% (SnPb) and 60%/40% (SnPb) are predominant formulations, and are commonly referred to as eutectic solder. lead free solder: A solder sphere which does not contain lead (Pb). NOTE Refer to J-STD-609 for leaded and lead free marking. PBGA: Plastic ball grid array package. Printed Ci
19、rcuit Board (PCB): Printed board that provides both point-to-point connections and printed components in a predetermined arrangement on a common base (also sometimes termed Printed Wiring Board). (Ref. IPC-T-50G) SAC: A type of lead-free solder made from tin, silver, and copper (Sn=S,Ag=A, Cu=C). (R
20、ef. IPC-7095B) surface mount process technology (SMT): A method of constructing electronic printed circuit boards in which components (small or large devices) are placed onto solder paste (or flux) in specified locations and exposed to reflow process window with varying sets of elevated temperature
21、and time that allows solder coalescence and metallization. solder void area: The area of the solder void region within the X-ray image of a BGA solder ball or joint. JEDEC Standard No. 217.01 Page 3 3 Informative reference documents J-STD-609, Marking and Labeling of Components, PCBs, and PCBAs to I
22、dentify Lad (Pb) Pb-Free and Other Attributes JESD16-A, Assessment of Average Outgoing Quality Levels in Parts Per Million (PPM) JESD47, Stress-Test-Driven Qualification of Integrated Circuits JESD22-B112, Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature IPC-A
23、-610D, Acceptability of Printed Circuit Assemblies IPC-7095B, Design and Assembly Process Implementation for BGAs IPC-T-50G, Terms and Definition for Interconnecting and Packaging Electronic Circuits JEDEC Standard No. 217 Page 4 4 Ball attach process flow Solder balls are attached by applying a flu
24、x/paste material on to the BGA pads, placing the solder balls on the pads, and reflowing the BGA package. The reflow process forms a metallurgical joint between the solder ball and the substrate ball pad. Alignment is a key parameter during ball placement to avoid missing solder balls or solder ball
25、s bridging. Figure 4-1 gives a sequential representation of the BGA ball attach process flow. Figure 4-1 BGA ball attach process flow diagram JEDEC Standard No. 217.01 Page 5 5 Types of solder voids For the sake of completeness, all six types of voids observed in solder joints are described in this
26、section, including potential voids that manifest after BGA type package are mounted onto a board. The individual characteristics of each of these voids are listed below. Macrovoids are the most common voids in solder joints. These are caused by volatile compounds that evolve during the soldering pro
27、cesses. These macrovoids generally do not affect the solder joint reliability unless they are present at interfacial regions in the solder joints where cracks typically propagate. This type of voids is within scope of this document. Planar Microvoids are a series of small voids, in relatively the sa
28、me plane, located at the interface between the PCB lands and the solder. These are caused by copper caves predominantly observed under immersion silver (ImAg) surface-finish coated lands. They do not affect initial product quality, but can affect long term solder joint reliability. They can be elimi
29、nated by strict control of the ImAg surface finish plating and etching materials and critical process parameters. Shrinkage Voids are caused by the shrinkage during solidification, mostly for SAC and other lead free solders. They do not generally appear near the solder-to-PCB land interface and do n
30、ot impair the solder joint reliability. These shrinkage voids can be minimized by increasing the cooling rate during soldering and avoiding disturbance to the joint while its solidifying. Micro-via Voids are caused by the presence of micro-vias designed in the PCB lands. Large micro-via voids, if lo
31、cated in solder joints in high stress areas of a package can impact solder joint reliability. Plating the micro-via shut, or filling it completely with solder paste by double printing can minimize the creation of these voids. IMC Microvoids occur within the intermetallic compound (IMC) formed betwee
32、n copper and high Sn solders, including SAC and SnPb solders. These IMC microvoids do not form immediately after the soldering process, but after aging at high temperatures or during temperature cycling of the solder joints. The true root cause is still under investigation, but a Kirkendall voiding
33、mechanism may play a part. These voids can affect solder joint reliability, particularly in instances when brittle fracture is initiated within the IMC during drop or mechanical shock to the solder joint. Pinhole Voids are caused by pinholes in the copper lands of the PCB. With sufficient quantity,
34、they can affect solder joint reliability. These voids are caused by entrapped PCB fabrication chemicals within these pinholes that volatilize during the reflow soldering process. The pinholes occur due to an excursion within the copper plating process at the PCB fabricator and can be eliminated by i
35、mproved copper plating process control systems. These type of voids are considered out-of-scope JEDEC Standard No. 217 Page 6 5 Types of solder voids (contd) Figure 5-1 illustrates all six types of voids and their typical size and location in a BGA solder joint. Figure 5-1 Typical size and location
36、of various types of voids in a BGA solder joint For this publication, focus is placed on macrovoids, because they are most likely to manifest prior to SMT process and can be identified by most metrologies. The other type of voids is noted for completeness, but out-of-scope due to metrology detection
37、 and void formation concerns. 6 Solder void metrologies 6.1 2-D X-ray 2-D X-ray is one of the metrologies being used to detect and measure the voids in BGA solder joints. There are a variety of 2-D X-ray tool vendors. Care must be taken to optimize the tool settings to achieve the best possible meas
38、urements. Generic guidelines for this technique are described below. JEDEC Standard No. 217.01 Page 7 6.1 2-D X-ray (contd) 6.1.1 Tool requirement/limitation The X-ray tube should be perpendicular to the test sample during image capture, as shown in Figure 6-1. Oblique viewing does not provide “true
39、” void %. The field of view may be modulated by adjusting the distance between the test sample and X-ray tube. Field of view ought to be set considering accuracy of the inspection as well as throughput requirements. Variations in the field of view that permits 3x3, 4x4 and 5x5 ball array are commonl
40、y reported. Figure 6-1 Illustration of X-ray setup and its orthogonal alignment to test sample To achieve the best possible contrast between BGA voids and the surrounding area for solder void detection, adjustments to the grey scale should be considered. Below are ranges of settings that may be util
41、ized as starting points. The settings are given in terms of % grey scale (black is 0, white is 100): Solderball = 36 to 48 % Background = 85 to 100 % The above settings can be achieved by adjusting the current and voltage on the X-ray tool. Figure 6-2 emphasizes the importance of proper contrast; vo
42、ids are barely visible in the left image, while the right image was collected after achieving the best possible contrast. JEDEC Standard No. 217 Page 8 6.1 2-D X-ray (contd) 6.1.1 Tool requirement/limitation (contd) (0% contrast) (30% gray) Figure 6-2 Example of contrasting in grey scaling (0% to 30
43、% gray) permitting detection of solder voids In general, 2-D X-ray metrology provides some advantages such as general availability, ease of operation, non-destructive nature to test samples, and faster throughput over other techniques like 3-D X-ray and cross-section. However, it has some limitation
44、s which are given in Table 6-1. Table 6-1 2-D X-ray Potential limitations Item Image Plated Thru Hole via interference. The red squares in the image at the right indicate where the software algorithm for automatic void calculation has incorrectly identified via hole outlines that intersect the BGA b
45、all outline as solder voids. This results in an over-estimation of the cumulative % void area within the BGA ball from the X-ray image. Interference of passive devices (like capacitors) with BGA solder joints. The software algorithm for automatic void calculation did not identify and measure the voi
46、ds in the solder ball images that intersect the chip capacitor image within the figure at the right. JEDEC Standard No. 217.01 Page 9 6.1 2-D X-ray (contd) 6.1.1 Tool requirement/limitation (contd) Table 6-1 2-D X-ray Potential limitations (contd) Item Image Before Measurement Image After Measuremen
47、t The entire void area is not being measured by the automated software algorithm. Edge areas in the solder ball image are incorrectly being measured as voids in the ball image. Voids in the edge areas of the solder ball image are being missed during measurement by the automated software algorithm. S
48、ome of the limitations can be attributed to software algorithms provided with the tools, while others are dependent on the type and location of solder voids or inherent to 2-D transmission X-ray technology itself. Nevertheless, 2-D X-ray metrology can be used in conjunction with stand-alone image an
49、alysis software applications. 6.2 3-D computer tomography X-ray 3-D- X-ray tomography can be used as an engineering tool to image, measure and locate solder joint voids. Tomography imaging involves three main steps: 1) Image acquisition (collect shadow images as the sample rotates through at least 180 degrees). 2) Software reconstruction that renders the 3-D volume 3) Inspection where the size, shape, location and dimensions of the solder joint may be established and measured. JEDEC Standard No. 217 Page 10 6.2 3-D computer tomography X-ray (contd) F
