1、JEDEC STANDARD Temperature, Bias, and Operating Life JESD22-A108D (Revision of JESD22-A108C, June 2005) NOVEMBER 2010 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors
2、level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting t
3、he purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve
4、 patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound a
5、pproach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance
6、 with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Sol
7、id State Technology Association 2010 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material
8、. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. Fo
9、r information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 JEDEC Standard No. 22-A108D Page 1 Test Method A108D (Revision of Test Method A108C) TEST METHOD A108D TEMPERATURE, BIAS, AND OPERATING LIFE (From J
10、EDEC Board Ballots JCB-99-89, JCB-99-89A, JCB-05-49, and JCB-10-60 formulated under the cognizance of JC-14.1 Committee on Reliability Test Methods for Packaged Devices.) 1 Scope This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simula
11、tes the devices operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality-related failures. The detailed use and
12、application of burn-in is outside the scope of this document. 1.1 Applicable documents JESD47, Stress-Test Driven Qualification of Integrated Circuits JEP122, Failure Mechanism and Models for Silicon Semiconductor Devices 2 Apparatus The performance of this test requires equipment that is capable of
13、 providing the particular stress conditions to which the test samples will be subjected. 2.1 Circuitry The circuitry through which the samples will be biased must be designed with several considerations: 2.1.1 Device schematic The biasing and operating schemes must consider the limitations of the de
14、vice and shall not overstress the devices or contribute to thermal runaway. 2.1.2 Power The test circuit should be designed to limit power dissipation such that, if a device failure occurs, excessive power will not be applied to other devices in the sample. 2.2 Device mounting Equipment design, if r
15、equired, shall provide for mounting of devices to minimize adverse effects while parts are under stress, (e.g., improper heat dissipation). JEDEC Standard No. 22-A108D Page 2 Test Method A108D (Revision of Test Method A108C) 2 Apparatus (contd) 2.3 Power supplies and signal sources Instruments (such
16、 as DVMs, oscilloscopes, etc.) used to set up and monitor power supplies and signal sources shall be calibrated and have good long-term stability. 2.4 Environmental chamber The environmental chamber shall be capable of maintaining the specified temperature within a tolerance of 5 C throughout the ch
17、amber while parts are loaded and unpowered. 3 Definitions 3.1 Maximum operating voltage The maximum supply voltage at which a device is specified to operate in compliance with the applicable device specification or data sheet. 3.2 Absolute maximum rated voltage The maximum voltage that may be applie
18、d to a device, beyond which damage (latent or otherwise) may occur; it is frequently specified by device manufacturers for a specific device and/or technology. 3.3 Absolute maximum rated junction temperature The maximum junction temperature of an operating device, beyond which damage (latent or othe
19、rwise) may occur; it is frequently specified by device manufacturers for a specific device and/or technology. NOTE Manufacturers may also specify maximum case temperatures for specific packages. 4 Procedure The sample devices shall be subjected to the specified or selected stress conditions for the
20、time and temperature required. 4.1 Stress duration The bias life duration is intended to meet or exceed an equivalent field lifetime under use conditions. The duration is established based on the acceleration of the stress (see JEP122). The stress duration is specified by internal qualification requ
21、irements, JESD47 or the applicable procurement document. Interim measurements may be performed as necessary per restrictions in clause 6. JEDEC Standard No. 22-A108D Page 3 Test Method A108D (Revision of Test Method A108C) 4 Procedure (contd) 4.2 Stress conditions The stress condition shall be appli
22、ed continuously (except during interim measurement periods). The time spent elevating the chamber to accelerated conditions, reducing chamber conditions to room ambient, and conducting the interim measurements shall not be considered a portion of the total specified test duration. 4.2.1 Ambient temp
23、erature Unless otherwise specified, the ambient temperature and bias for high temperature stress shall be adjusted to result in a minimum junction temperature of the devices under stress of 125 C. Unless otherwise specified, the ambient temperature for low temperature stress shall be a maximum of 10
24、 C. 4.2.2 Operating voltage Unless otherwise specified, the operating voltage should be the maximum operating voltage specified for the device unless the conditions of 4.2.1 cannot be met. A higher voltage is permitted in order to obtain lifetime acceleration from voltage as well as temperature; thi
25、s voltage must not exceed the absolute maximum rated voltage for the device, and must be agreed upon by the device manufacturer. 4.2.3 Biasing configurations Biasing configurations may be bias stress (static or pulsed) or operating stress (dynamic). Depending upon the biasing configuration, supply a
26、nd input voltages may be grounded or raised to a maximum potential chosen to ensure a stressing temperature not higher than the maximum-rated junction temperature. Device outputs may be unloaded or loaded, to achieve the specified output voltage level. If a device has a thermal shutdown feature it s
27、hall not be biased in a manner that could cause the device to go into thermal shutdown. 4.2.3.1 High temperature forward bias (HTFB) The HTFB test is configured to forward bias major power handling junctions of the device samples. The devices may be operated in either a static or a pulsed forward bi
28、as mode. Pulsed operation is used to stress the devices at, or near, maximum-rated current levels. The particular bias conditions should be determined to bias the maximum number of the solid state junctions in the device. The HTFB test is typically applied on power devices, diodes, and discrete tran
29、sistor devices (not typically applied to integrated circuits). JEDEC Standard No. 22-A108D Page 4 Test Method A108D (Revision of Test Method A108C) 4.2 Stress conditions (contd) 4.2.3.2 High temperature operating life (HTOL) / Low temperature operating life (LTOL) The HTOL / LTOL test is configured
30、to bias the operating nodes of the device samples. The devices may be operated in a dynamic operating mode. Typically, several input parameters may be adjusted to control internal power dissipation. These include: supply voltages, clock frequencies, input signals, etc., that may be operated even out
31、side their specified values, but resulting in predictable and nondestructive behavior of the devices under stress. The particular bias conditions should be determined to bias the maximum number of potential operating nodes in the device. The HTOL test is typically applied on logic and memory devices
32、. The LTOL test is intended to look for failures caused by hot carriers, and is typically applied on memory devices or devices with submicron device dimensions. 4.2.3.3 High temperature reverse bias (HTRB) The HTRB test is configured to reverse bias major power handling junctions of the device sampl
33、es. The devices are characteristically operated in a static operating mode at, or near, maximum-rated breakdown voltage and/or current levels. The particular bias conditions should be determined to bias the maximum number of the solid state junctions in the device. The HTRB test is typically applied
34、 on power devices. 4.2.3.4 High temperature gate bias (HTGB) The HTGB test biases gate or other oxides of the device samples. The devices are normally operated in a static mode at, or near, maximum-rated oxide breakdown voltage levels. The particular bias conditions should be determined to bias the
35、maximum number of gates in the device. The HTGB test is typically used for power devices. 5 Cool-down Devices on high temperature stress shall be cooled to 55 C or lower before removing the bias. Cooling under bias is not required for a given technology if verification data is provided by the manufa
36、cturer. The interruption of bias for up to one minute, for the purpose of moving the devices to cool-down positions separate from the chamber within which life testing was performed, shall not be considered removal of bias. All specified electrical measurements shall be completed prior to any reheat
37、ing of the devices, except for interim measurements subject to restrictions of clause 6. NOTE Bias refers to application of voltage to power pins. JEDEC Standard No. 22-A108D Page 5 Test Method A108D (Revision of Test Method A108C) 6 Measurements The measurements specified in the applicable life tes
38、t specification shall be made initially, at the end of each interim period, and at the conclusion of the life test. Interim and final measurements may include high temperature testing. However, testing at elevated temperatures shall only be performed after completion of specified room (and lower) te
39、mperature test measurements. After interim testing, bias shall be applied to the parts before heat is applied to the chamber, or within ten minutes of loading the final parts into a hot chamber. Electrical testing shall be completed as soon as possible after removal of bias from devices and no longe
40、r than 96 hours for high voltage devices (defined as 10V) or 168 hours for all other devices. If the availability of test equipment or other factors make meeting this requirement difficult, bias must be maintained on the devices either by extending the Bias Life Stress or keeping the devices under b
41、ias at room temperature until these time windows can be met. If the devices have been removed from bias and the time window is exceeded, the stress must be resumed for the duration specified in Table 1 prior to completion of the measurements. After an interim measurement, the stress shall be continu
42、ed from the point of interruption. The time window and the high temperature testing restrictions of this clause need not be met if verification data for a given technology is provided. Table 1 Additional Stress Requirements for parts not tested within time window Hours by which time window has been
43、exceeded 0 but 168 168 but 336 336 but 504Other Additional stress hours required prior to performing electrical test 24 48 72 24 hours for each 168 hours (week) by which the time window has been exceeded 7 Failure criteria A device is defined as a failure if it does not meet the requirements of the
44、applicable procurement document. JEDEC Standard No. 22-A108D Page 6 Test Method A108D (Revision of Test Method A108C) 8 Summary The following items shall be specified in the applicable life test specification: a) Special preconditioning, when applicable. b) Stress temperature (chamber ambient) c) St
45、ress duration. d) Stress mounting, if special instructions are needed. e) Stress condition and stress circuit schematic. f) Sample size and acceptance number. g) Time to complete endpoint measurements, if other than specified in clause 6. h) Operating mode. i) Interim read points, if required. j) Ma
46、ximum junction temperature during stress. k) Verification data if cool-down under bias is not performed. JEDEC Standard No. 22-A108D Page 7 Test Method A108D (Revision of Test Method A108C) Annex A (informative) Differences between JESD22-A108D and JESD22-A108C This table briefly describes the chang
47、es made to JESD22-A108D, compared to its predecessor, JESD22-A108C (June 2005). Page Term and description of change 5 Revised time window requirements in section 6. 5 Revised table 1 to align with section 6. A.1 Differences between JESD22-A108C and JESD22-A108-B This table briefly describes the chan
48、ges made to JESD22-A108C, compared to its predecessor, JESD22-A108-B (December 2000). Page Term and description of change 5 Revised wording in end of clause 6 and replaced note with table 1. 6 Corrected 8(g) to refer to clause 6 instead of paragraph 5. JEDEC Standard No. 22-A108D Page 8 Test Method
49、A108D (Revision of Test Method A108C) Standard Improvement Form JEDEC JESD22-A108D The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 2500 Wilson Blvd. Suite 220 Arlington, VA 22201-3834 Fax: 703.907.7583 1. I recommend changes to the f
