1、 JEDEC STANDARD Temperature, Bias, and Operating Life JESD22- A108E (Revision of JESD22-A108D, November 2010) DECEMBER 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Dire
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7、for alternative contact information. Published by JEDEC Solid State Technology Association 2016 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individua
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9、tion 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 22-A108E Page 1 Test Method A108E (Revision of Test Method A108D) TEST METHOD A108E TEMPERATURE, BIAS, AND OPERATING LIFE (From JEDEC Boa
10、rd Ballots JCB-99-89, JCB-99-89A, JCB-05-49, JCB-10-60, and JCB-16-47 formulated under the cognizance of JC-14.1 Committee on Reliability Test Methods for Packaged Devices.) 1 Scope This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It sim
11、ulates the devices operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality-related failures. The detailed use a
12、nd application of burn-in is outside the scope of this document. 1.1 Applicable documents JESD47, Stress-Test Driven Qualification of Integrated Circuits JEP122, Failure Mechanism and Models for Silicon Semiconductor Devices 2 Apparatus The performance of this test requires equipment that is capable
13、 of providing the particular stress conditions to which the test samples will be subjected. 2.1 Circuitry The circuitry through which the samples will be biased must be designed with several considerations: 2.1.1 Device schematic The biasing and operating schemes must consider the limitations of the
14、 device and shall not overstress the devices or contribute to thermal runaway. 2.1.2 Power The test circuit should be designed to limit power dissipation such that, if a device failure occurs, excessive power will not be applied to other devices in the sample. 2.2 Device mounting Equipment design, i
15、f required, shall provide for mounting of devices to minimize adverse effects while parts are under stress, (e.g., improper heat dissipation). JEDEC Standard No. 22-A108E Page 2 Test Method A108E (Revision of Test Method A108D) 2 Apparatus (contd) 2.3 Power supplies and signal sources Instruments (s
16、uch as DVMs, oscilloscopes, etc.) used to set up and monitor power supplies and signal sources shall be calibrated and have good long-term stability. 2.4 Environmental chamber The environmental chamber shall be capable of maintaining the specified temperature within a tolerance of 5 C throughout the
17、 chamber while parts are loaded and unpowered. 3 Definitions 3.1 Maximum operating voltage The maximum supply voltage at which a device is specified to operate in compliance with the applicable device specification or data sheet. 3.2 Absolute maximum rated voltage The maximum voltage that may be app
18、lied to a device, beyond which damage (latent or otherwise) may occur; it is frequently specified by device manufacturers for a specific device and/or technology. 3.3 Absolute maximum rated junction temperature The maximum junction temperature of an operating device, beyond which damage (latent or o
19、therwise) may occur; it is frequently specified by device manufacturers for a specific device and/or technology. NOTE Manufacturers may also specify maximum case temperatures for specific packages. 4 Procedure The sample devices shall be subjected to the specified or selected stress conditions for t
20、he time and temperature required. 4.1 Stress duration The bias life duration is intended to meet or exceed an equivalent field lifetime under use conditions. The duration is established based on the acceleration of the stress (see JEP122). The stress duration is specified by internal qualification r
21、equirements, JESD47 or the applicable procurement document. Interim measurements may be performed as necessary per restrictions in clause 6. JEDEC Standard No. 22-A108E Page 3 Test Method A108E (Revision of Test Method A108D) 4 Procedure (contd) 4.2 Stress conditions The stress condition shall be ap
22、plied continuously (except during interim measurement periods). The time spent elevating the chamber to accelerated conditions, reducing chamber conditions to room ambient, and conducting the interim measurements shall not be considered a portion of the total specified test duration. 4.2.1 Ambient t
23、emperature Unless otherwise specified, the ambient temperature and bias for high temperature stress shall be adjusted to result in a minimum junction temperature of the devices under stress of 125 C. Unless otherwise specified, the ambient temperature for low temperature stress shall be a maximum of
24、 10 C. 4.2.2 Operating voltage Unless otherwise specified, the operating voltage should be the maximum operating voltage specified for the device unless the conditions of 4.2.1 cannot be met. A higher voltage is permitted in order to obtain lifetime acceleration from voltage as well as temperature;
25、this voltage must not exceed the absolute maximum rated voltage for the device, and must be agreed upon by the device manufacturer. 4.2.3 Biasing configurations Biasing configurations may be bias stress (static or pulsed) or operating stress (dynamic). Depending upon the biasing configuration, suppl
26、y and input voltages may be grounded or raised to a maximum potential chosen to ensure a stressing temperature not higher than the maximum-rated junction temperature. Device outputs may be unloaded or loaded, to achieve the specified output voltage level. If a device has a thermal shutdown feature i
27、t shall not be biased in a manner that could cause the device to go into thermal shutdown. 4.2.3.1 High temperature forward bias (HTFB) The HTFB test is configured to forward bias major power handling junctions of the device samples. The devices may be operated in either a static or a pulsed forward
28、 bias mode. Pulsed operation is used to stress the devices at, or near, maximum-rated current levels. The particular bias conditions should be determined to bias the maximum number of the solid state junctions in the device. The HTFB test is typically applied on power devices, diodes, and discrete t
29、ransistor devices (not typically applied to integrated circuits). JEDEC Standard No. 22-A108E Page 4 Test Method A108E (Revision of Test Method A108D) 4.2 Stress conditions (contd) 4.2.3.2 High temperature operating life (HTOL) / Low temperature operating life (LTOL) The HTOL / LTOL test is configur
30、ed to bias the operating nodes of the device samples. The devices may be operated in a dynamic operating mode. Typically, several input parameters may be adjusted to control internal power dissipation. These include: supply voltages, clock frequencies, input signals, etc that may be operated even ou
31、tside their specified values, but resulting in predictable and nondestructive behavior of the devices under stress. The particular bias conditions should be determined to bias the maximum number of potential operating nodes in the device. The HTOL test is typically applied on logic and memory device
32、s. The LTOL test is intended to look for failures caused by hot carriers, and is typically applied on memory devices or devices with submicron device dimensions. 4.2.3.3 High temperature reverse bias (HTRB) The HTRB test is configured to reverse bias major power handling junctions of the device samp
33、les. The devices are characteristically operated in a static operating mode at, or near, maximum-rated breakdown voltage and/or current levels. The particular bias conditions should be determined to bias the maximum number of the solid state junctions in the device. The HTRB test is typically applie
34、d on power devices. 4.2.3.4 High temperature gate bias (HTGB) The HTGB test biases gate or other oxides of the device samples. The devices are normally operated in a static mode at, or near, maximum-rated oxide breakdown voltage levels. The particular bias conditions should be determined to bias the
35、 maximum number of gates in the device. The HTGB test is typically used for power devices. 5 Cool-down Devices on high temperature stress shall be cooled to 55 C or lower before removing the bias. Cooling under bias is not required for a given technology if verification data is provided by the manuf
36、acturer. The interruption of bias for up to one minute, for the purpose of moving the devices to cool-down positions separate from the chamber within which life testing was performed, shall not be considered removal of bias. All specified electrical measurements shall be completed prior to any rehea
37、ting of the devices, except for interim measurements subject to restrictions of clause 6. NOTE Bias refers to application of voltage to power pins. JEDEC Standard No. 22-A108E Page 5 Test Method A108E (Revision of Test Method A108D) 6 Measurements The measurements specified in the applicable life te
38、st specification shall be made initially, at the end of each interim period, and at the conclusion of the life test. Interim and final measurements may include high temperature testing. However, testing at elevated temperatures shall only be performed after completion of specified room (and lower) t
39、emperature test measurements. After interim testing, bias shall be applied to the parts before heat is applied to the chamber, or within ten minutes of loading the final parts into a hot chamber. Electrical testing shall be completed as soon as possible after removal of bias from devices and no long
40、er than 96 hours for high voltage devices (defined as 10 volts) or 168 hours for all other devices. If the availability of test equipment or other factors make meeting this requirement difficult, bias must be maintained on the devices; this may be either at the stress temperature or room temperature
41、 and the bias may be reduced to nominal voltage from any accelerated voltage in use for stress. . If the devices have been removed from bias and the time window is exceeded, the stress must be resumed for the duration specified in Table 1 prior to completion of the measurements. After an interim mea
42、surement, the stress shall be continued from the point of interruption. The time window and the high temperature testing restrictions of this clause need not be met if verification data for a given technology is provided. Table 1 Additional Stress Requirements for parts not tested within time window
43、 Hours by which time window has been exceeded 0 but 168 168 but 336 336 but 504 Other Additional stress hours required prior to performing electrical test The lesser of 24 OR 50% of the stress interval since the last test readout The lesser of 48 OR 50% of the stress interval since the last test rea
44、dout The lesser of 72 OR 50% of the stress interval since the last test readout The lesser of 24 hours for each 168 hours (week) by which the time window has been exceeded OR 50% of the stress interval since the last test readout 7 Failure criteria A device is defined as a failure if it does not mee
45、t the requirements of the applicable procurement document. JEDEC Standard No. 22-A108E Page 6 Test Method A108E (Revision of Test Method A108D) 8 Summary The following items shall be specified in the applicable life test specification: a) Special preconditioning, when applicable. b) Stress temperatu
46、re (chamber ambient) c) Stress duration. d) Stress mounting, if special instructions are needed. e) Stress condition and stress circuit schematic. f) Sample size and acceptance number. g) Time to complete endpoint measurements, if other than specified in clause 6. h) Operating mode. i) Interim read
47、points, if required. j) Maximum junction temperature during stress. k) Verification data if cool-down under bias is not performed. JEDEC Standard No. 22-A108E Page 7 Test Method A108E (Revision of Test Method A108D) Annex A (informative) Differences between JESD22-A108E and its predecessors These ta
48、bles briefly describe most of the differences between the text of this standard, JESD22-A108E, and its predecessors JESD22-A108D (November 2010), JESD22-A108C (June 2005), and JESD22-A108B (December 2000. A.1 Differences between JESD22-A108E and JESD22-A108D Clause Term and description of change 6 C
49、larified allowance to remain on bias at non-accelerated conditions and revised restress requirements. 6 Capped restress requirements for short stress intervals. A.2 Differences between JESD22-A108D and JESD22-A108C Clause Term and description of change 6 Revised time window requirements in clause 6. 6 Revised table 1 to align with clause 6. A.3 Differences between JESD22-A108C and JESD22-A108-B Clause Term and description of change 6 Revised wording in end of clause 6 and replaced note with table 1. 8 Corrected 8(g) to refer to clause 6 instead of paragraph 5. JEDEC St
