1、JEDEC STANDARD Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Stress Test JESD22-A117C (Revision of JESD22-A117B, March 2009) OCTOBER 2011 JEDEC Solid State Technology Association NOTICE JEDEC standards and publications contain material that has been prepa
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10、VA 22201-2107 or call (703) 907-7559 JEDEC Standard No. 22-A117C Page 1 ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION STRESS TEST (From JEDEC Board Ballot JCB-11-7x, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Method an
11、d Packaged Devices.) 1 Scope This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected
12、life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are s
13、pecified in JESD47 or may be developed using knowledge-based methods as in JESD94. This stress test does not replace other stress test qualification requirements. The program/erase endurance and data retention test for qualification and monitoring, using the parameter levels specified in JESD47, is
14、considered destructive. Lesser test parameter levels (e.g., of temperature, number of cycles, retention bake duration) may be used for screening as long as these parameter levels have been verified by the device manufacturer to be nondestructive; this can be performed anywhere from wafer level to fi
15、nished device. 2 Terms and definitions 2.1 EEPROM A reprogrammable read-only memory in which the cells at each address can be erased electrically and reprogrammed electrically. NOTE The term EEPROM in this document includes all such memories, including FLASH EEPROM integrated circuits and embedded m
16、emory in integrated circuits such as Erasable Programmable Logic Devices (EPLDs) and microcontrollers. Destructive-read memories such as ferroelectric memories, in which the read operation re-writes the data in the memory cells, are beyond the scope of this document. 2.2 Data pattern The mix of 1s a
17、nd 0s in the memory and their physical or logical positions. NOTE A device may be single-bit-per-cell (SBC), meaning that one physical memory cell stores a “0” or a “1”, or multiple-bits-per-cell (MBC), meaning that one cell stores typically two bits of data: “00”, “01”, “10”, or “11”. In some MBC m
18、emories, the two bits represent logically-adjacent bit-pairs in each byte of data. For example, a byte containing binary data 10110001 would correspond to four physical cells with data 2301 in base-four logic. In other MBC memories, the two bits may represent bits in entirely different address locat
19、ions. For an SBC memory a physical checkerboard pattern consists of alternating 0s and 1s, with each 0 surrounded by 1s on either side and above and below; a logical checkerboard pattern consists of data bytes AAH or 55H in which each 0 is logically adjacent to 1s. In some qualifications only logica
20、l positions may be known. Test Method A117C (Revision of Test Method A117B) JEDEC Standard No. 22-A117C Page 2 2.3 Endurance The ability of a reprogrammable read-only memory to withstand data rewrites and still comply with its specifications. NOTE 1 EEPROM device specifications often require an eras
21、e step before reprogramming data; in this case a data rewrite includes both erase and programming steps, which together are called a program/erase cycle. Direct-write memories allow data to be written directly over old, without an erase; in this case the use of the generic term “program/erase cycle”
22、 will refer to a single rewrite with no erase. For SBC memories that require an erase step, one program/erase cycle consists of programming cells (typically to “0”) and then erasing (“1”). For the comparable MBC case, a cycle would consist of programming cells (to “0”, “1”, or “2”) and then erasing
23、(“3”). NOTE 2 Endurance stressing consists of performing multiple rewrites in succession, and the data pattern or patterns for these rewrites must be chosen. There is no one data pattern or set of patterns that is worst-case for all failure mechanisms. For example, for floating-gate memories a fully
24、-programmed pattern is worst-case for charge transfer, but a physical checkerboard pattern is worst-case for spurious programming of adjacent cells, and a mostly-erased pattern may be worst-case for mechanisms related to erase-preconditioning algorithms. For MBC memories, programming to the highest
25、state is worst-case for charge transfer, but intermediate-state cells may experience more programming time and also have less sensing margin. Finally, in some memories, the margin of a cell is influenced by the data states of the physically adjacent cells. 2.4 Endurance failure A failure that arises
26、 during endurance cycling. NOTE 1 An endurance failure occurs if the device fails to complete the program or erase operations within the datasheet-specified times or if it fails to meet any of its other datasheet requirements as a result of program/erase cycling. A program operation that results in
27、incorrect data being stored in the device counts as an endurance failure. However, if an error-management method such as an error-correction code is built into the device or specified to be applied by the system, then failure is taken to occur only if the error is not properly managed by the specifi
28、ed method. NOTE 2 Certain products are specified to operate with either internal or external bad-block management system (BBM). When the BBM system detects an endurance failure it directs the data to another (spare) block and removes the address of the failing block from an appropriate address table
29、. An endurance failure of such product is taken to occur when a pre-set number of spare blocks of the product had been consumed within that product datasheet specified cycle count. NOTE 3 A number of distinct failure mechanisms are responsible for endurance failures, and in general these are acceler
30、ated in different ways by temperature and other adjustable qualification parameters. For example, in floating-gate memories failure may be caused by charge trapping (normally accelerated by lower temperatures) in the charge transfer dielectric or by oxide rupturing (normally accelerated by higher te
31、mperatures) in the transfer dielectric or in peripheral dielectrics. Test Method A117C (Revision of Test Method A117B) JEDEC Standard No. 22-A117C Page 3 2.5 Failure The loss of the ability of a component to meet the electrical or physical performance specifications that (by design or testing) it wa
32、s intended to meet. NOTE 1 The term failure is often qualified by an adjective describing the type of failure. For example, a component is a functional failure if it fails to function and a parametric failure if it functions but does not meet a datasheet specification for a parameter such as power c
33、onsumption. Endurance and retention failures are defined in 2.4 and 2.7. NOTE 2 Failures may be firm or transient. For the purpose of this standard, a firm failure is a component that fails sometime during a reliability stress and continues to fail at the final test at the end of that same stress. A
34、 transient failure is a component that fails during a reliability stress but passes in the final test at the end of that stress. 2.6 Retention The ability of the EEPROM cell to retain data over time. NOTE 1 The term data retention may refer to the ability of a device to retain data in the unbiased s
35、tate, but the term will sometimes be used to include the ability to retain data under bias. The term “disturb” refers unambiguously to the ability of an EEPROM cell to retain data over time under bias. For example, read disturb refers to the ability of an EEPROM cell to retain data after being read
36、a given number of times. A detailed discussion of disturbs is beyond the scope of this document. NOTE 2 Retention stressing consists of writing a data pattern into a device and then verifying that the pattern is intact after a specified time at a specified temperature. There is no single data patter
37、n that is worst-case for all retention mechanisms, cell designs, or process architectures. There are generally some failure mechanisms which primarily affect programmed cells and some which primarily affect erased cells, and there are also failure mechanisms which depend on the data in adjacent cell
38、s. 2.7 Retention failure A change of stored data by one bit or more detected when the device is read according to data sheet specifications. NOTE 1 If an error-management method such as an error-correction-code is built into the device or specified to be applied by the system, then failure is taken
39、to occur only if the error is not properly managed by the specified method. NOTE 2 A number of distinct failure mechanisms are responsible for retention failures, and in general these are accelerated in different ways by temperature and other adjustable qualification parameters. For example, in floa
40、ting-gate memories, failure may occur due to defects that allow charge to leak through the transfer dielectric or by the detrapping of charge in the transfer dielectric; the former can be weakly accelerated or even decelerated by high temperature, and the latter can be highly temperature-accelerated
41、. Test Method A117C (Revision of Test Method A117B) JEDEC Standard No. 22-A117C Page 4 2.8 Uncorrectable bit-error rate (UBER) A metric for data corruption rate, equal to the number of data errors per bit read after applying any specified error-correction method. NOTE 1 The uncorrectable bit error r
42、ate is calculated from the following equation: readbitsofnumbercumulativeerrorsdataofnumbercumulativeUBER (1) For non-error-corrected devices, any data bit in error counts as a data error. For error-corrected devices, any codeword or sector (as defined in the product data sheet) returning incorrect
43、data after applying the specified error-correction scheme counts as a data error. Transient data errors, such as data errors that occur at a given program/erase cycle but not at later ones, are counted as data errors. Standard statistical confidence levels may be applied to the numerator. The cumula
44、tive number of bits read is the sum of all bits of data read back from the device, with multiple reads of the same memory bit counting as multiple bits read. For example, if a 1-Gb device is read 10 times, then there would be 10Gb bits read. NOTE 2 Some devices may be specified to have a certain UBE
45、R value, and in this case the qualification must determine that the device meets the UBER specification. Section 5 discusses details regarding calculation of the UBER value. 3 Apparatus The apparatus required for this test shall consist of a controlled temperature chamber capable of maintaining the
46、specified temperature conditions to within 5 C. Sockets or other mounting means shall be provided within the chamber so that reliable electrical contact can be made to the device terminals in the specified circuit configuration. Power supplies and biasing networks shall be capable of maintaining the
47、 specified operating conditions throughout the test. Also, the test circuitry should be designed so that the existence of abnormal or failed devices will not alter the specified conditions for other units on test. Care should be taken to avoid possible damage from transient voltage spikes or other c
48、onditions that might result in electrical, thermal or mechanical overstress. Test Method A117C (Revision of Test Method A117B) JEDEC Standard No. 22-A117C Page 5 4 Procedure Qualification specifications, including those in JESD47, commonly require that some devices undergo both endurance stressing a
49、nd, after being cycled, retention stressing. There may also be retention requirements for uncycled devices. Qualification specifications commonly call for endurance stressing to be performed at multiple temperatures within the datasheet range. Qualification specifications commonly call for retention stressing to be performed both at elevated temperatures, such as 125 C, and room temperature. Figure 1 schematically illustrates the flow, with references to the paragraphs describing the procedure. Figure 1 Schematic Flow Perform one P/E Cycle, verified per 4.1.2 and using dat
