1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD232NOVEMBER 2015JEDECSTANDARDGRAPHICS DOUBLE DATA RATE(GDDR5X) SGRAM STANDARD NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and app
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9、ct:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240SArlington, Virginia 22201or call (703) 907-7559JEDEC Standard No. 232-i-Contents1 SCOPE 12 GDDR5X SGRAM STANDARD OVERVIEW .22.1 Features 23 FUNCTIONAL DESCRIPTION .33.1 Functional Overview 33.2 Signal State Terminology .43.
10、3 Clocking .43.4 Addressing .73.5 Bank Groups 103.6 Address Bus Inversion (ABI) .123.7 Read and Write Data Bus Inversion (DBI) 133.8 Error Detection Code (EDC) . 153.9 VREFC and VREFD . 193.10 Temperature Sensor 223.11 Duty Cycle Corrector 234 MODE REGISTERS 244.1 Mode Register 0 .264.2 Mode Registe
11、r 1 .284.3 Mode Register 2 .304.4 Mode Register 3 .324.5 Mode Register 4 .334.6 Mode Register 5 354.7 Mode Register 6 364.8 Mode Register 7 .374.9 Mode Register 8 .394.10 Mode Register 9 .404.11 Mode Register 10 .404.12 Mode Register 11 .414.13 Mode Register 12 to 14 .414.14 Mode Register 15 .425 DE
12、VICE INITIALIZATION .435.1 Power-up Sequence 435.2 Initialization with Stable Power . 455.3 Vendor ID 466 TRAINING .486.1 Interface Training Sequence .486.2 Address Training 496.3 WCK2CK Training 506.3.1 WCK Alignment at Pin Mode 536.3.2 WCK Auto Synchronization .536.3.3 WCK2CK Training Examples .53
13、6.3.4 Read and Write Latencies .556.4 READ Training 566.4.1 LDFF Command .576.4.2 RDTR Command 606.5 WRITE Training 616.5.1 WRTR Command .627 OPERATION .647.1 Commands 647.2 Command, Address And Write Data Input Timings 65JEDEC Standard No. 232-ii-7.3 No Operation (NOP) 657.4 Mode Register Set .657.
14、5 Row Activation 667.6 Write (WOM)697.6.1 DQ Write Preamble 767.7 Write Lower And Upper Bytes (WOML/WOMU)777.8 Write Data Mask (WDM/WSM).797.9 READ 887.9.1 DQ Read Preamble .957.9.2 READ with RDQS Mode .967.10 Precharge 977.10.1 Auto Precharge .987.11 Refresh 987.11.1 Refresh Command .987.11.2 Per-B
15、ank Refresh Command 997.12 Self Refresh . 1017.12.1 Hibernate Self Refresh .1047.12.2 Partial Array Self Refresh .1057.13 Power-Down 1057.14 Low Frequency Modes .1087.15 Clock Frequency Change Sequence .1087.16 Command Truth Tables .1098 OPERATING CONDITIONS .1138.1 Absolute Maximum Ratings 1138.2 P
16、ad Capacitances 1138.3 Package Electrical Specification.1148.4 Package Thermal Characteristics 1148.5 Electrostatic Discharge Sensitivity Characteristics 1158.6 DC 16n prefetch architecture with 512 bit per array read or write access; burst length 16 DDR mode: Double Data Rate (DDR) data (WCK); 8n p
17、refetch architecture with 256 bit per array read or write access; burst length 8 16 internal banks 4 bank groups for tCCDL= 3 tCKand 4 tCK Programmable read latency: 5 to 36 tCK; programmable write latency: 1 to 7 tCK Write data mask function via address bus (single/double/quad byte mask) Data bus i
18、nversion (DBI) programmable CRC write latency = 7 to 14 tCK Low Power modes RDQS mode on EDC pins On-chip temperature sensor with read-out Auto an access starts at a selected location and consists of a total of sixteen data words in QDR mode and eight data words in DDR mode. Accesses begin with the
19、registration of an ACTIVATE command, which is then followed by a READ or WRITE com-mand. The address bits registered coincident with the ACTIVATE command and the next rising CK_c edge are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRIT
20、E command and the next rising CK_c edge are used to select the bank and the column loca-tion for the burst access.This specification includes all features and functionality required for JEDEC GDDR5X SGRAM devices. Users benefit from knowing that any system design based on the required aspects of the
21、 specification are supported by all GDDR5X SGRAM vendors; conversely users seeking to use any superset specifications bear the responsibility to verify support with individual vendors.JEDEC Standard No. 232Page 43.2 SIGNAL STATE TERMINOLOGYThe GDDR5X SGRAM will be operated in both ODT enable (termin
22、ated) and ODT disable (unterminated) modes. For highest data rates it is recommended to operate in the ODT enable mode. ODT disable mode is designed to reduce power and may operate at reduced data rates. There exist situations where ODT enable mode can not be guaranteed for a short period of time, f
23、or example during power-up.Four terminologies define the state of a device pin (GDDR5X SGRAM or controller) during operation. The state of the bus will be determined by the combination of the device pins connected to the bus in the sys-tem. For example, with GDDR5X it is possible for the device pin
24、to be tristated while the controller pin is High or ODT. In both cases the bus would be High if the ODT is enabled.Device pin signal level: High: a device pin drives the Logic “1” state. Low: a device pin drives the Logic “0” state. High-Z: a device pin is tristate. ODT: a device pin terminates with
25、 ODT setting, which could be terminating or tristate depending on mode register setting.Bus signal level: High: one device on the bus is High and all other devices on bus are either ODT or High-Z. The voltage level on the bus would be nominally VDDQ. Low: one device on the bus is Low and all other d
26、evices on bus are either ODT or High-Z. The voltage level on the bus would be nominally VOL(DC) if ODT is enabled, or VSSQif High -Z. High-Z: all devices on the bus are High-Z. The voltage level on bus is undefined as the bus is floating. ODT: at least one device on the bus is ODT and all others are
27、 High-Z. The voltage level on the bus would be nominally VDDQ.3.3 CLOCKINGThe GDDR5X SGRAM operates from a differential clock CK_t and CK_c. Commands are registered at every rising edge of CK_t. Addresses are registered at every rising edge of CK_t and every rising edge of CK_c.The data interface us
28、es two differential forwarded clocks WCK_t and WCK_c, each associated with two data bytes. WCK_t and WCK_c are continuously running and operate at twice the frequency of the com-mand/address clock (CK_t/CK_c). A PLL/DLL is associated with each WCK pair. The use of the PLL/DLL is mandatory in QDR mod
29、e and optional in DDR mode. QDR mode uses a quad data rate data interface and a 16n-prefetch architecture for DQ/DBI_n, and a double data rate data interface and 8n-prefetch architecture for EDC. The PLL/DLL generates four equally spaced clock edges per WCK clock cycle. QDR means that four DQ/DBI_n
30、data words per WCK cycle are registered at these internally generated clock edges. DDR means that two EDC data words per WCK cycle are registered at every second of these internally generated clock edges. DDR mode uses a double data rate data interface and an 8n-prefetch architecture for DQ/DBI_n/ED
31、C. DDR means that the data is registered at every rising edge of WCK_t and rising edge of WCK_c.JEDEC Standard No. 232Page 53.3 CLOCKING (contd)Table 1 and Figure 1 illustrate the clock and interface signal relationship for both QDR and DDR operating modes.Table 1 Example Clock and Interface Signal
32、Frequency RelationshipPIN QDR MODE DDR MODE UNITCK_t, CK_c 1.5 1.5 GHzCommand 1.5 1.5 Gbps/pinAddress 3.0 3.0 Gbps/pinWCK_t, WCK_c 3.0 3.0 GHzDQ, DBI_n 12.0 6.0 Gbps/pinEDC 6.0 6.0 Gbps/pinCK_cCK_tCOMMANDWCK_tWCK_cDQ, DBI_n(QDR Mode)DQ, DBI_n(DDR Mode)EDC(QDR + DDR Modes)ADDRESSNOTE 1 Figure 1 shows
33、 the relationship between the data rate of the buses and the clocks and is not a timing diagram.Figure 1 GDDR5X Clocking and Interface RelationshipClock PhaseOscillatorQDADD/CMDADD/CMDDRAM DATA DQearly/lateReceiverD QWCKintDQDRAM PLL/DLLQDDQPhase detector/logicearly/late fromController GDDR5X SGRAMP
34、LL/DLLclockData Tx/RxWCK_t/(3 GHz)CK_t/CK_c(1.5 GHz)CMD sampled by CK_t/CK_c as SDRADD sampled by CK_t/CK_c as DDRADD/CMD centered with CK_t/CK_ccalibration dataaccumulatorControllerClock PhaseController(QDR mode:corecoreQDR mode: 3.0 GHzD QWCK2CKAlignmentTo EDC pin/2WCK_cDDR mode: 1.5 GHz(DDR mode
35、only)12 Gbps)(DDR mode:6 Gbps)QDcoreJEDEC Standard No. 232Page 63.3 CLOCKING (contd)Figure 2 Block Diagram of an Example Clock SystemJEDEC Standard No. 232Page 73.4 ADDRESSINGGDDR5X SGRAMs use a double data rate address scheme to reduce pins required on the device as shown in Table 2. The addresses
36、should be provided in two parts; the first half is latched on the rising edge of CK_t along with the command pins such as RAS_n, CAS_n and WE_n; the second half is latched on the next rising edge of CK_c.The use of DDR addressing allows all address values to be latched in at the same rate as the SDR
37、 com-mands. All addresses related to command access have been positioned for latching on the initial rising edge for faster decoding.Table 2 Address PairsClock Address PinsBA3 BA2 BA1 BA0 A14 A12 A11 A10 A9 A8A3 A4 A5 A2 A15 A13 A6 A0 A1 A7The addressing includes support for 4 Gb to 16 Gb densities
38、and both QDR and DDR operating modes as shown in Table 3. Table 3 Addressing SchemeDensity 4 Gb 6 Gb 8 Gb 12 Gb 16 GbI/O Configuration x32 x16 x32 x16 x32 x16 x32 x16 x32 x16Rising CK_tRising CK_cRow address A0A12 A0A13 A0-A13 A0-A14 A0A13 A0A14 A0A14 A0A15 A0A14 A0A15Column address DQ15:0QDR Mode A
39、0A5 A0A5 A0A5 A0A5 A0A5DDR Mode A0A6 A0A6 A0A6 A0A6 A0A6Column address DQ31:16QDR Mode A7,A9,A12A15 A7,A9,A12A15 A7,A9,A12A15 A7,A9,A12A15 A7,A9,A12A15DDR Mode A7,A9,A12A15,A6 A7,A9,A12A15,A6 A7,A9,A12A15,A6 A7,A9,A12A15,A6 A7,A9,A12A15,A6Bank address BA0BA3 BA0BA3 BA0BA3 BA0BA3 BA0BA3Autoprecharge
40、A8 A8 A8 A8 A8Page Size 4K 2K 4K 2K 4K 2K 4K 2K 4K 2KRefresh 16K/32ms 16K/32ms 16K/32ms 16K/32ms 16K/32msRefresh period 1.9us 1.9us 1.9us 1.9us 1.9usNOTE 1 The burst order is fixed for Reads and Writes, and the GDDR5X SGRAM does not assign column address bits to distinguish between the UIs of a burs
41、t. A memory controller may internally assign such column address bits but these column address bits are not transmitted on the colum address bus to the GDDR5X SGRAM.NOTE 2 Row address range with A13:12 = 11 (x32 mode) or A14:13 = 11 (x16 mode) is not present for 6 Gb density. Row address range with
42、A14:13 = 11 (x32 mode) or A15:14 = 11 (x16 mode) is not present for 12 Gb density. ACT/RD/WR commands to these memory locations are illegal.NOTE 3 Two column addresses CAL and CAU with shared bank addresses are provided with each WRITE and READ command.NOTE 4 For complete details on refresh refer to
43、 the vendors datasheets for values for refresh interval, refresh period and tRFCas tRFCwill scale with density and is vendor specific.JEDEC Standard No. 232Page 83.4 ADDRESSING (contd)Two column addresses with a common bank address are provided with each READ and WRITE com-mand, allowing two pseudo-
44、independent memory accesses with 32 bytes access granularity in QDR oper-ating mode and 16 bytes access granularity in DDR operating mode: The lower column address (CAL) is associated with DQ15:0 and received on addresses A5:0. The upper column address (CAU) is associated with DQ31:16 and received o
45、n addresses A15:12, 9, 7.GDDR5X SGRAMs addressing is transparent between QDR and DDR operating modes: data can be writ-ten in QDR operating mode with a single BL=16 WRITE burst, and read in DDR operating mode with two BL=8 READ bursts, and vice versa. Column address A6 is evaluated in DDR operating
46、mode only; it can be considered the LSB and selects between the data corresponding to the first half of a BL=16 burst (UI 07) with A6 being set Low, and the data corresponding to the second half of a BL=16 burst (UI 815) with A6 being set High.Figure 3 illustrates the addressing in QDR and DDR opera
47、ting modes assuming the same column addresses CAL and CAU for lower and upper data bytes. This is equivalent to accesses using a single col-umn address, however, it is required to provide both CAL and CAU along with the READ or WRITE com-mand.Case 1: Single READ/WRITE burst in QDR Mode (BL16) with C
48、AL = CAUDQ31:16 DQ15:0BL16 BL16CALCA6=XCAUCA6=XCase 2: Two READ/WRITE bursts in DDR Mode (BL8) with CAL = CAUCAUCA6=0CALCA6=0BL8 BL8DQ31:16 DQ15:0CAUCA6=1CALCA6=1BL8 BL8Figure 3 Column Accesses with Identical Lower and Upper Column AddressesJEDEC Standard No. 232Page 93.4 ADDRESSING (contd)Figure 4
49、illustrates the addressing in QDR and DDR operating modes assuming different column address for lower and upper bytes. This corresponds to two pseudo-independent memory accesses with 32 bytes access granularity in QDR operating mode and 16 bytes in DDR operating mode. It is pointed out that both accesses share the bank address and therefore access the same open row in that bank. Case 3: One READ/WRITE burst in QDR Mode with CAL CAUCAUCA6=0CALCA6=0BL8BL8DQ31:16 DQ15:0CAUCA6=1CALCA6=1B
