1、 JEDEC STANDARD DDR4 NVDIMM-N Design Specification JESD248A (Revision of JESD248, September 2016) MARCH 2018 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and
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9、rth 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 248A Page 1 DDR4 NVDIMM-N DESIGN SPECIFICATION (From JEDEC Board Ballot JCB-17-40, formulated under the cognizance of the JC-45.6 Subcommittee on Hyb
10、rid Modules.) Scope 1This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface
11、 consisting of DRAM that is made non-volatile through the use of NAND Flash. NVDIMM-N modules adhere to the Byte Addressable Energy Backed Interface specification. The JESD245B Byte Addressable Energy Backed Interface specification provides detailed logical behavior, interface, and register definiti
12、ons. These DDR4 NVDIMM-Ns are intended for use as persistent memory when installed in PCs. An NVDIMM-N is either an: NVLRDIMM-N: a Load Reduced DIMM (LRDIMM) compliant with JESD21C Page 4.20.27 DDR4 SDRAM Load Reduced DIMM Design specification except as specified in this standard; or NVRDIMM-N: a Re
13、gistered DIMM (RDIMM) compliant with JESD21C Page 4.20.28 DDR4 SDRAM Registered DIMM Design Specification except as specified in this standard. System interface constraints are included which provide an initial basis for DDR4 NVDIMM-N designs. Modifications to these constraints may be required to me
14、et all system timing, signal integrity and thermal requirements for PC4-1600, PC4-1866, PC4-2133, PC4-2400, PC4-2666 and PC4-3200 support. All DDR4 NVDIMM-N implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design. The annex fo
15、r each raw card will have specific entries to indicate DIMM operation and voltage levels. This specification works in conjunction with: JESD21C, Page 4.1.2.L-5 Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules (DDR4 SPD Document Release 5) JESD21C, Page 4.20.27 DDR4 SDRAM Load Reduced DIM
16、M Design Specification (August 2015) JESD21C, Page 4.20.28 DDR4 SDRAM Registered DIMM Design Specification (August 2015) JESD79-4B, DDR4 SDRAM (June 2017) JESD245B, Byte Addressable Energy Backed Interface (July 2017) JEDEC Standard No. 248A Page 2 1 Scope (contd) Table 1 DDR4 Product Family Attribu
17、tes DIMM Organization x72 ECC Notes DIMM Dimensions (nominal) 133.35 mm x 31.25 mm Refer to MO-309 133.35 mm x 18.75 mm Refer to MO-309 Pin Count 288 DDR4 SDRAMs Supported 4Gb, 8Gb, 16Gb 78/106 ball FBGA package for x4 and x8 devices. Refer to MO-207: variations DT-z, DW-z Capacity 4GB, 8GB, 16GB, 3
18、2GB, 64GB, 128GB SDRAM width x4, x8 Serial Presence Detect, Thermal Sensor (SPD-TSE) 512 byte TSE2004av specifications Voltage Options VDD: PC4 - 1.2 Volt 5%, PC4L - TBD VPP: 2.5 Volt +10%, -5% The VPP supply has VSS as its return path. VPP is a separate supply. VDDSPD: 2.5 Volt 10% The VDDSPD suppl
19、y has VSS as its return path. VDDSPD is separate from the VPP power plane. VDDSPD is shared between the SPD-TSE and the RCD (register). The RCD only supports 2.5V. V_12: +12 Volt 15% The +12 V supply has VSS as its return path. +12 V is required for NVDIMM-N operation. Interface 1.2 V signaling JEDE
20、C Standard No. 248A Page 3 Environmental Requirements 2288-pin Registered DDR4 NVDIMM-N modules are intended for use in a variety of environments including standard office environments that have limited capacity for heating and air conditioning. Table 2 Environmental Parameters Symbol Parameter Rati
21、ng Units Notes TOPR Operating Temperature (ambient) 0 to +55 C 3 HOPR Operating Humidity (relative) 10 to 90 % TSTG Storage Temperature -50 to +100 C 1 HSTG Storage Humidity (without condensation) 5 to 95 % 1 PBAR Barometric Pressure (operating LOW: no Autoprecharge). A10 is sampled during a Prechar
22、ge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC_n Input VDD Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fl
23、y) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. JEDEC Standard No. 248A Page 6 RESET_n CMOS Input VDD Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operat
24、ion. DQ Input/ Output VDD Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific data sheets
25、 to determine which DQ is used. DQS0_t-DQS17_t, DQS0_c-DQS17_c Input/ Output VDD Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS_t is paired with differential signals DQS_c, respectively, to provide differential pair
26、 signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended. TDQS9_t-TDQS17_t, TDQS9_c-TDQS17_t Input VDD Provides a dummy load for x8 based NVDIMM-Ns where mixed populations of X4 and x8 based NVDIMM-Ns are present. DBI0_n-DB
27、I8_n Input/ Output VDD Provides for data bus inversion. Only possible for x8 based NVDIMM-Ns and where only x8 based NVDIMM-Ns are on a channel. DM0_n-DM8_n Input VDD Provides for masking of a byte on WRITE commands to the SDRAMs. Only possible for x8 based NVDIMM-Ns and where only x8 based NVDIMM-N
28、s are on a channel. PAR Input VDD Command and Address Parity Input: DDR4 Supports Even Parity check in SDRAMs with MR setting. Once its enabled via Register in MR5, then SDRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A0. Input parity should be maintained at
29、 the rising edge of the clock and at the same time with command and one or more DIMM slots. The motherboard shall include a pull-up resistor sized to meet the SAVE_n signal characteristics defined in Table 6 (e.g., a 2.5 V supply) for the selected number of DIMM slots (e.g., keeping the resulting vo
30、ltage below the maximum Vio and supporting a varying number of loads from zero to the number of DIMM slots sharing the signal). If SAVE_n is used as a module output the resistor shall be connected to a power supply that ramps at the same time as the V_12 supply pin. NOTE The JESD21C Page 4.20.28 (RD
31、IMM) and Page 4.20.27 (LRDIMM) specifications require V_12 to ramp up prior to VPP, VDD, and VTT. The NVDIMM-N module shall not include a pullup resistor on the SAVE_n signal. Table 6 defines signal characteristics for the SAVE_n signal at the NVDIMM-N module edge connector. Table 6 SAVE_n Signal Ch
32、aracteristics Symbol Parameter Condition Min Max Units Vio Input or output range -0.3 3.0 V Vih Input high voltage 1.7 3.0 V Vil Input low voltage -0.3 0.7 V Vol Output low voltage 3 mA sink current 0.4 V Tr Input rise time 1 1 s Tf Input fall time 2 50 ns Cin Input Capacitance 3 30 pF 1 Tr is from
33、Vil (max) to Vih (min). 2 Tf is from Vih (min) to Vil (max). 3 Trace capacitance shall be included in Cin. JEDEC Standard No. 248A Page 11 3.2 SAVE_n signal (contd) Figure 1 defines the relationships between Vio, Vih, Vil, Tr, Tf, tSAVE_PW_LOW (see JESD245B), tSAVE_PW_HIGH (see JESD245B), and tSRE_H
34、old (see JESD245B). Figure 1 Voltage and Timing Relationships The host controller shall tristate SAVE_n during normal operation and during power on initialization. To request that the NVDIMM-N perform a Catastrophic Save operation, the host controller shall: 1) complete any outstanding operations to
35、 the NVDIMM-Ns SDRAM (e.g., flush write buffers); 2) put the NVDIMM-Ns SDRAM into self-refresh; and 3) assert SAVE_n as defined in JESD245B (e.g., drive low for the specified pulse width or toggle multiple times). The NVDIMM-N module shall tristate SAVE_n during normal operation and during power on
36、initialization. If enabled (see JESD245B), the NVDIMM-N module shall drive SAVE_n low while it is performing a Cata-strophic Save operation as defined in JESD245B and shall tristate SAVE_n after the Catastrophic Save operation completes. Time Voltage Vih tSRE_Hold Vil Tr Tf tSAVE_PW_LOW tSAVE_PW_HIG
37、H Vio JEDEC Standard No. 248A Page 12 Power Details 44.1 DIMM Voltage Requirements The DIMM voltage requirements and the SDRAM voltage requirements are not identical. There must be some allowance for a small voltage drop across the DIMM. Table 7 defines the requirements for the Host at the DIMM sock
38、et. Some modules have lower current requirements. Any specific module must meet the SDRAM, DDR4RCD01/02, and DDR4DB01/02 voltage requirements for its worst case supply currents. Table 7 DDR4 NVDIMM-N DC Operating Voltage1,2,3 - 1.2V interface Symbol Parameter Voltage Rating (Volts) Maximum Expected
39、Current Power State Minimum Typical4 Maximum VDD Supply Voltage 1.16 1.21 1.26 11.7 A Operational VPP Activation Supply Voltage 2.41 2.50 2.75 3.75 A Operational VTT5 Termination Voltage 0.565 0.605 0.64 0.75 A Operational VTT at termination Termination Voltage 0.95 x VDDmin6/2 (0.542) - 1.05 x VDDm
40、ax6/2 (0.662) 0.75 A Operational VDDSPD SPD-TSE Supply Voltage 2.41 2.5 2.75 0.75 A Operational 12 V Power for NVDIMM-N non-volatile technologies 10.2 12.0 13.8 1.17 A Operational 5.8 12.0 13.8 1.4 A Backup power off (optional)7 5.8 12.0 13.8 500 A Idle power off (optional)7 1. 20 MHz bandwidth limi
41、ted measurement for all voltages in the table. 2. Voltages are measured at the DIMM gold fingers. 3. The SDRAM specification must be met and take precedence over this document. 4. Typical voltage is platform dependent, suggested value only. 5. At the DIMM interface VTT is the only voltage during nor
42、mal operating conditions that can both source and sink current. 6. SDRAM VDD specification range. 7. 12 V Backup power off and Idle power off requirements must be met if module backup power supplied through 12 V. 4.1.1 VTT Range At the termination Vtt must be within; 1. 0.95 x Vddmin/2 = (0.60V 0.05
43、8V) = 0.542 2. = 0 ms = 0 ms = 0 ms See SDRAM Specification Clock CKE d RCD (Register) Specification JEDEC Standard No. 248A Page 14 4.3 Recommended Power Down Sequence Figure 3 Graphical View of Recommended Power Down Sequence The normal power down sequence shown in Figure 3 requires the voltage re
44、lationships established during power on be maintained. Vft (the Feed through voltage) is defined as the voltage delta between Vss and the associated power plane with no power applied to that plane. The absolute value of this voltage must remain less than 200 mV (|Vft| 0.20 V), which is less than the
45、 300 mV DRAM ramp reference level for start or end of voltage ramp. 4.4 +12 V Power The +12 volt power source is required for NVDIMM-N modules while system power is on to support technologies other than DDR4 SDRAM. Homogeneously populated DRAM modules (i.e., UDIMMs, RDIMMs, and LRDIMMs) may be inser
46、ted into sockets that provide 12 V support. The +12 Volts supply must meet the requirements of Section 4.1 and 4.2. 12 V Backup power off and Idle power off requirements must be met if module backup power supplied through V_12. The NVDIMM-N is powered from backup power when the system power is off a
47、nd a SAVE backup operation has been initiated. Any module which uses 12 V must not interfere with the power sequence(s) of modules that do not support 12 Volts. 12 V shall remain valid during reduced power modes except it may remain valid during self-refresh. The specific load requirements during th
48、ese modes are product specific. JEDEC Standard No. 248A Page 15 Component Details 5MO-207 allows a maximum SDRAM package height of 21.0 mm. The maximum package size is not required for DDR4 NVDIMM-Ns. The larger the SDRAM package the farther it must be placed from the edge connector and the longer t
49、he DQ bus must be. Minimizing the SDRAM package size to what is actually required improves signal integrity. Decoupling is improved if the capacitors are placed closer to the SDRAM balls. Power delivery is improved with a reduction in width of the SDRAMs to what is actually required. See 6.7.4 for target SDRAM package size. Figure 4 shows the mechanical information for the DDR4 SDRAM component. To use a smaller SDRAM component some or all of the mechanical support balls may be omitted. Figure 4 DIMM Ball Patterns for DDR4 SDRAM Compone
