1、JEDEC STANDARD Standard Data Transfer Format Between Data Preparation System and Programmable Logic Device Programmer i JESD3-C (Revision of JESD3-B) JUNE 1991 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT EIA JESD3-C 94 W 3234b00 0555088 bTT W NOTICE JEDEC Standards and Publications cont
2、ain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDE Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufac
3、turers and purchases, facilitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from
4、 manufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or internationally. JEDEC Standards and Publications are adopted without
5、 regard to whether their adoption may involve patents or articles, materials, or processes. By such action, JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publications. The information included in JEDEC S
6、tandards and Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard or Publication may be further processed and ultimately became an
7、 EIA Standard. Inquiries, comments, and suggestions relative to the content of this JEDEC Standard should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Pennsylvania Ave., N.W., Washington, D.C. 20006. Published by %LECTRONIC INDUSTRIES ASSOCIATION 1994 Engineering Departmen
8、t 2001 Pennsylvania Ave., N.W. Washington, D.C. 20006 PRICE: Please refer to the current Catalog of EU, JEDEC, and TIA STANDARDS and ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-7179) International (303-397-7956) Printed in U.S.A. All rights reserved EIA J
9、ESD3-C 94 3234600 0555089 536 PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the EL4 and may not be reproduced without permission, Organizations may obtain permission to reproduce a iimited number of copies through entering into a license agreement with the EL% For information, contac
10、t: EIA Engineering Publications Offce 2001 Pennsylvania Ave., N.W. Washington, D.C. 20006 (202)457-4963 EIA JESD3-C 74 m 3234b00 0555090 258 m JEDEC Standard No 3-C STANDARD DATA TRANSFER FORMAT BETWEEN DATA PREFARAXON SYSTEM AND PROGRAMMABLE LOGIC DEVICE PROGRAMMER corns 1 INTRODUCTION 1.1 purpoSed
11、scOpe 1 1.3 Cues to October 1983 Standard 2 1.4 Changes preload test vectors . 2 1.6 Additions to MD3-B that implement JESD3-C . 3 1.2 Summary of pq-2 ad Testrng Fields 2 1.5 Addition of Regi- Observation Vector 3 2 SPECIAL NOTATIONS AND DEFINITIONS 2.1 Notation Conventions 3 2.2 BNF Rules and Defin
12、ition . 4 2.3 PLD Register Numbering . 5 3 TRANSMISSION PROTOCOL 3.1 Protocol Syntax . 5 3.2 Cornputmg the Transmission Checksum 6 3.3 Disabling the Transmission Checksum 6 5 COMMENT AND DEFINITION FIELDS 5.1 specification 7 5.2 Note (N) 8 5.3 k!Vice ) 8 5.4 values (QF,QP, QV) . 8 6 DEVICE PROGRAMMI
13、NG FIELDS 6.1 Syntax and Overview . 9 6.2 Fuse Default State (F) . 9 6.4 Fuse Ch it has been eliminated to ensure the format is device and techology independent. 5.4 Values (QF. QP. QV) The Q field expresses values or limits that must be provided to the receiving equipment. Thne subfields are define
14、d: the F subfield for the number of fuses, the P subfield for number of pins or test conditions in the test vector, and the V subfield for the maximum number of test vectors. These values enable the receiving device to eaiciently allocate memory and the second number is a pinout code. The field is p
15、laced in front of any F, L, or H fields. The J field is optional. Syntax for JEDEC device identification field: device a test condition may be applied to pin S before or &er pin 4.) The P field indicates an alternative correspondence between the t& conditions and the pin numbers. Each package pin, i
16、ncluding noncomects, must be represented by a number in the P field Example: P1234561415161778910111213181920* VOO01 111000HLH* v0002 100000H* Vector1willapply111000topins1through6andHLHHtopins14through17.Pins7through13and18through 20 are not tested (N). 7.5 Test Conditions The test condition logic
17、levels are defined by the device technology (e.g. Tn. CMOS, ECL). The O and 1 test conditions apply a steady state logic level to the device pin. The device tester should allow the applied input conditions to be ovenidden by bidirectional (inputloutput) device pins. The X or dont care test condition
18、 applies the default level defined by the X field. The F test condition applies a high impedance to the device pin. The sequence that the input conditions are applied to the device is not defined, so multiple vectors should be used when the sequence is important. The following example ensures that p
19、in 4 transitions to a logic level 1 before pin 3. v01 xxoov* v02 xxo 1 -* V03 XXI I-* EIA JESD3-C 94 m 3234600 0555307 381 JEDEC Standard NO. 3-C Page 16 The test conditions 2 through 9 apply a non standard or super voltage to the device. lbs may be used to access special test modes. The levels are
20、defined for each device and test vectors utiiizing super voltages codd damage “second source“ devices. The C test condition applies a logic level O until all other inputs are stable (and device timing specifications are met) then switches to a logic level 1 and returns to a logic level O before the
21、outputs are tested. The K test condition goes from 1 to O to 1 in a similar manner. For devices more than one clock input, multiple test vectors should be used to ensure the proper clocking sequence. The U test condition applies a logic level O until all other inputs are stable and internal set-up t
22、imes met, then switches to a logic level 1 and remains at that level. This test condition should be used for any clock input that must make a smgle O to 1 transition. It is differentiated hm the 1 test condition in that the device tester does not allow the input condition to be overridden by bidirec
23、tional device pins, thus allowing the U test condition to make a much faster transition. The D test condition is analogous to the U test condition except it applies a logic level 1 until all other inputs are stable and intemal Set-up times met, then switches to a logic level O and remains at that le
24、vel. The N test condition is used for power pins, output pins not tested, and non connected device pins. Atter all inputs have stabilized, including clock, the output test are perfomed. The L test for a logic level O and the H test for a logic level 1. The 2 test condition test that an output is in
25、a high impedance condition. 7.6 Register Preload Register Preload means forcing or “jam loading“ a regista to a known state. Three types of register preloading are defined: “in-circuit“, “output register“, and “buried register“. “In-circuit“ preload is accomplished with dedicated input pins and/or i
26、ntemai control logic and uses normal in-circuit logic levels. The standard input and clock test conditions may be used to preload the registers in these devices. The “output register“ and “buried register“ preload operations use non standard levels or “super voltages“ to access special modes to prel
27、oad the registers. Because teq algorithms are unique for each device, the following generic methods may allow one set of test vectors to work with “second source“ devices. The device programmer/tester will apply the specific superalgorithm for each device type. EIA JESD3-C 94 m 3234600 0555108 218 J
28、EDEC Standard No -3-C Pape li 7.6.1 P Preload Vector A P preload vector is used to preload PLDs with output registers connected to device pins. The P preload vector is used to set the pins to a desired state. The P symbol is applied to the clock pins controlling the registers. The vector values corr
29、espondmg to the output registers must be 0 or 1. The value specified in the P vector is the value that is desired at the output device pm &er the preload operation. Example 1. Preload a 16R4 with the P preload symbol. 11111111112 := V -umber deIimiteP T Qest conditions :N-2 * The T vector numbered V
30、xxxx (in decimal) will be a vector containing the symbols 0-9 and A-Y. The T test vector length is equal to the number of pins in the device. The vector is terminated by an asterisk. The first vector element Erom the left will be the T test condition symbol. The second element is an alphanumeric cha
31、racter used to identify the register group to obsave. Register groups will be numbered from 0-9, A-Y. The character 2 is reserved for future use. The remaining test conditions in the vector refer to the states of up to N-2 registers in the group identified by the group number, where N is the number
32、of pins on the device. The allowed test conditions are I, W, T, & W. For example, if there are 8 registers in a 20-pin PD, then these 8 registers are assigned to group number O. Within pup O, the 8 registers will be assigned a unique number starting from l. This register number is used to calculate
33、the registers positlon in the observation vector. VOO01 TLHHHHLLLLMJNNNNNNMJ. G 20-pin PLD The test vector in the above example is used to observe 8 registers in a 20-pin PLD. Note that these registers can be input, output, or internal registers. The next vector elements after the T and group number
34、 refer to the expected states to be tested on the registers. If some registers are not to be tested, an X (or dont care) symbol should be used. If there are more vector positions than registem in the PLD, then the rest of the vector is filled with the N symbol. Example 1: Observing a device with 12
35、registers. All 12 registem can be tested in one T vector. VOO01 TOHHHLLLHLHLHLNNNNNIP Example 2: Observing the last 6 registers in a 20-pin PLD with 26 registers. The status of the 19th and 20th registers is ignored by using the X test condition. The last 6 registers are contained in register group
36、1. Example 3: Test registas 17 to 23 on a 20-pin device with 26 registers. VOO01 TOP* V0002 TlHHHLHXXXNNNNNNNNNN* Vector VOO01 will observe registers 17-18 (in group O), and V0002 will observe registas 19-23 (group 1). The other registers will be ignored EIA JESD3-C 94 m 3234600 0555112 749 m JEDEC
37、Standard No 3-C Pape 11 The group number for the Xth register and the position of the Xth register within an observation vector can be calculated by the following formulas: GROW-NO = (X-1) div (PINS-2) POSONINVECTOR = X - (PINS-2)*GROuP_NO) + 2 where: PINS = # of device pins div = integer division (
38、fractions are truncated) For example, if a 20-pin PLD has 40 registers, then the 3 1st register will belong in group l. GROUP-NO = (3 1 - 1) div (20-2) =30div18 =I POSITION-IN-VECTOR =31-(18*1)+2 x31 -18+2 = 15 VOO01 TlXXXXXXXXXXXXlXXXXX* h h h register 3 1 in vector group number 1 position 15 When
39、a T vector is used in a JEDEC file, the QP field must specify all the device pins. The P (pin order sequence) will not affect the T vector. For the T vector, L and H should be used to specify register test values. The registers are preloaded Using the 0 and 1 symbols in a B or P preload vector. 8 PR
40、OGRAMMERlTESTER OPTIONS 8.1 Security Fuse (G) The security Ws) of certain logic devices may be enabled for programming by sending a 1 in the G field. The security fuse prevents the reading of the fuse states. Syntax for the Security Fuse Field: := G 4inarydigip *I Example: G1 Enable security fuse pr
41、ognunming. EIA JESD3-C JEDEC Standard NO. 3-C Page 22 8.2 Signature Analysis Test (S, R, T) Signature Analysis tests are specified by the S, R, and T fields. The S field defines the starting vector for the test. The possible states are O and 1. The R field contains the resulting vector or test-sum.
42、The T field denotes the number of test cycles to be run. Syntax for Signature Analysis Test: := R QlexdigiW3 *I qest cycle := T aumm * N := number of pins on device Example: soloO0loo0olllooollllollo* RSBCD34A7* TO1 * 8.3 Access Time (A) The A field defines the propagation delay for test vectors in
43、one nanosecond incrments. This field may include optional subfields. Syntax for Access Time ) * Example: A25* MD25 9 EXAMPLES 9.1 Data File Examples 4Tx U1000 11111011111111111111111111111011111111111111111111111111 11101111111111111111111111110000000000000000000000000000 010101110111101111111111111
44、10000OOOOO000OOOOOOO0000o0o 0000000000000000000000om00o00ooomoomoooo0000omo 0101011110111011111111111111OOOOOOOOOOOOO00OOOO00m00 00000000000000000000OOOOOOOOOOOOOOOOOOOO 010101110111011111111111111100ooo0000OOOOOOOOOO00 00000000000000000000OOOOOOOOOOOOOOOOOOOOO* “X5718 EIA JESD3-C 94 m 3234600 05551
45、14 JEDEC Standard No 3-C Pagc 23 Example 1. Minimum file for device programmer as defined by Jedec Standard Na 3-A, October 1983. File for PLD 12% Created on 8-Feb-85 3:05PM 6809 memory decode 123-0017-001 Joe Engineer Advanced Logic Corp * QF0448* FO* m 1111101111111111111111111111* LO28 1011111111
46、111111111111111111* M56 lllOllllllllllllllllllllllll* L1120101011101111011111111111111* L2240101011110111011111111111111* L3360101011101110111111111111111* C 124E* Example 2. Data file for device programming. File for PLD 1258 Created on 8-Feb-85 3:OSPM 6809 memory decode 1230017-001 Joe weer Advanc
47、ed Logic COQ QP20* QV8* VOO01 OOOOOOMCXNXYXHHHLXXN* v0002 OlOOOOXXXNXXXHHHWCXN* v0003 lOOOOOXXXNXXXHHHLXXN* VOO04 110000X* V“5 11 lOOOXXXNXXXHLHHXXN* VOO06 11 lOIOXXXNXXXHHHHXXN* V0007 1 1 1 100XXXNXXXHHLHXXN V0008 11 11 IOXXXNXXXLHHHXXN. Example 3. Data File for device testing. File for PLD 12S8 Cr
48、eated on 8-Feb-85 3:05PM 6809 memory decode 123-0017-001 Joe Engineer Advanced Logic Corp * QP20 N Number of pins* QF0448 N Number of fuses* QVS* N Number of vectors* G1 N Program security fuse* FO* N Default fse state* xo* N Default test condition* N Fuse RAM Data. LOOOO 111110111111111111111111111
49、1 l0lllllll1llllllllllllllllll 1110111111111111111111111111* LO1 12 ololollIollIlollllllllllllll* L0224 0101011ll0111011111111111111* L0336 0101011101110111111111111111* EIA JESD3-C 94 3234600 0555115 458 m JEDEC Standard NO. 3-C Page 24 N Test Vectors* v0001 OOOOOOXXXMCXXHHHLXXN. v0002 OlO000XXXNXXX”LXXN* v0003 IOO* VOO04 llOOOoXXXNXXXHHHLXXN* v0005 11 1000xxxNx“LHHxxN* VOO06 11 lOlOXXXNX”HXXN* v0007 11 1100” V0008 11 11 IO-* N Fuse RAM checksum* C124E* N Signature Analysis test information* TO1 S000OOOOOOOOOOOOOOOOO* R95E4B822* Example 4. Data File for
