1、EINJEDEC STANDARD General Guidelines for Designing Test Structures for the Wafer-Level Testing of Thin Dielectrics EINJESD35-1 (Addendum Na 1 to EIAIJESD35) SEPTEMBER 1995 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT EIA JESD35-L 95 3234600 0563204 677 NOTICE EIA Engineering Standards an
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10、1 GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS CONTENTS Page . Foreword 111 1 Scope 1 2 Introduction 1 3 Sources of error in testing thin oxides 3.1 Test equipment 3.2 MOS properties 3.3 Series resistance 3.4 Environment/external factors 3.5 Parasi
11、tics 3.6 Damage 4 Electrical model 9 5 Test structure design considerations 10 6 Example test structure 14 7 References 14 Annexes 16 A 16 B 17 EIA JESD35-L 95 3234600 0563207 386 M ADDENDUMNo. 1 EINESD3 5- 1 EIA JESD35-1 95 3234600 0563208 212 U ADDENDUMNo. 1 EINJESD NO. 35-1 GENERAL GUIDELINES FOR
12、 DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS FOREWORD This addendum includes test structure development methodology, criteria, and examples to supplement JESD3 5. JESD35 describes procedures developed for estimating the overall integrity of thin oxides and as a tool for
13、 driving constant improvement in the thin oxide manufacturing process in the MOS integrated circuit manufacturing industry. Two test procedures are included in JESD35: a voltage-ramp (V-Ramp) and a current-ramp (J-Ramp). The development methodology, criteria, and examples of structures given herein
14、are general in purpose. It is important to realize that these procedures should not be interpreted as a means of predicting MOS integrated circuit failure rates but rather for quick evaluation control techniques. Thus, no acceptance or rejection criteria are specified in association with these proce
15、dures. The material contained in this publication was formulated under the cognizance of JEDEC JC- 14.2 Committee and approved by the Engineering Department Executive Committee (EDEC). . -111- EIA JESD35-L 75 3234600 0563207 153 W ADDENDUMNo. 1 EINJESD NO. 35-1 -iv- EIA JESD35-L 95 3234600 0563230 9
16、70 ADDENDUMNo. 1 Page 1 EWJESD35-1 GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS (From Council Ballot JCB-95-01 formulated under the cognizance of JEDEC JC-14.2 on Wafer Level Reliability) 1 Scope This addendum expands the usefulness of the JEDEC St
17、andard No. 35 (JESD35) by detailing the various sources of measurement error that could affect the test results obtained by the ramped tests described in the JESD35. Each source of error is described and its implications on test structure design is noted. This document can be used as a guide when de
18、signing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests. 2 Introduction The JESD35 describes voltage and current ramp tests for characterizing the integrity of thin dielectrics in MOS microe
19、lectronics. Two parameters, the breakdown electric field and the charge density to breakdown, are typically extracted fiom the test results and used as a measure of dielectric quality. The validity and accuracy of these parameters are dependent on the layout of the thin oxide test structure, test eq
20、uipment accuracy, and environmental conditions. It is therefore important to understand the various sources of error that can be introduced by the above factors. This document describes in detail the sources of error that can be encountered by test equipment, MOS properties, series resistance, envir
21、onment, parasitics, and structure damage when testing thin dielectrics. An electrical model of the thin oxide test structure is provided and recommendations for its design are given. 3 Sources of error in testing thin oxides 3.1 Test equipment Carefiil analysis and characterization of test equipment
22、 are necessary. Review and verification of the test equipment specifications will aid in program development. Deviations due to equipment can then be understood. EIA JESD35-L 95 3234600 05b32LL 807 ADDENDUMNo. 1 Page 2 EWJESD35-1 Measurement speed: The minimum measurement rate is o ce every 50 milli
23、sec nds, but since the last time period is ignored, measuring eveq 50 milliseconds can lead to obtaining a value that is significantly lower than the true qbd (i.e., if the capacitor did not break until 49 milliseconds after the step, the reported qbd will be .O49 times the current density less than
24、 actual qbd). The accuracy of the measurement can be greatly increased by measuring more often. Overshoot: When forcing a current, some instrumentation will overshoot the voltage needed to force the specified current. This overshoot can damage the capacitor and lead to an artificially low qbd and vb
25、d reading. The overshoot usually is a percentage of the step, small steps have a distinct advantage in reducing the amount of overshoot. 3.2 MOS properties The actual voltage sustained across the oxide under test may differ from the applied gate voltage due to gate-electrode work function difference
26、s and possible depletion in the gate electrode when polysilicon is used. The actual breakdown voltage of the oxide may therefore be greater than or less than the measured breakdown voltage. The work function difference, ms, between the gate electrode material and the silicon substrate is dependent o
27、n the gate electrode material and the doping level in the silicon substrate. A typical work function difference for an aluminum gate on n-type silicon with a substrate doping of 10l6 cm-3 is approximately -0.25 V. Heavily doped polysilicon is extensively used in place of aluminum for the gate electr
28、ode material. Typical values for the work function difference of various gate electrode metals and degeneratively doped polysilicon on silicon substrates can be found in i. If the polysilicon is not degeneratively doped then ms is also a function of the doping activation level in the polysilicon. De
29、pletion in the polysilicon gate electrode can also affect the actual voltage applied across the gate dielectric. The amount of depletion depends on the substrate doping in the silicon, the doping activation level in the polysilicon, the oxide thickness, and the applied gate voltage. Very high levels
30、 of dopants at the poly-oxide interface are required to suppress poly-gate depletion effects, especially for thin gate dielectrics. A more detailed discussion of poly-gate depletion effects can be found in 2-51. A formal derivation of the work function differences for n/p -type polysilicon gate mate
31、rial over n/p-type silicon substrate can be found in annex A. ADDENDUMNo. 1 EWJESD35-1 Page 3 3.3 Series resistance One of the potential problems involved in designing MOS capacitors for ramp testing (either voltage or current ramp) is that series resistance could lead to erroneous voltage or curren
32、t estimates due to voltage drops and joule heating. Series resistance can come from the measurement equipment, including probe resistance and contact resistance between the probes and the pads of the test structure, contact resistance between the chuck and substrate, as well as from the test structu
33、re itself. There are two key questions that must be answered before the design of a particular structure can be evaluated. The first question is, what is the maximum tolerable voltage error associated with the series resistance? The second question is, how does one calculate the series resistance of
34、 a given structure? If the answers to these questions are known, then a particular structure can be evaluated, and the design iterated if needed. The test structure will be the focus of attention in this section. Fundamentally, there are three distinct resistive paths within the structure, namely to
35、pside routing (such as metal or poly lines and vias), bottom Si (including wells, diffiisions, epi layers, and bulk substrate), and a distributed resistance associated with the capacitor structure itself This distributed resistance causes different regions of the gate oxide to be exposed to differen
36、t voltages, for the same applied voltage. For a given structure, the series resistance associated with routing and the bottom Si can be estimated from the design rule parameters, such as sheet resistances, via resistances, etc. The effect of the distributed resistance is more difficult to estimate b
37、ecause it is inherently geometry dependent. A simple approximate model will be presented here, which can be used for test capacitor design. It is derived with reference to a particular geometry, but can be adapted to other geometries of interest. Figure 3.1 is a sketch of the top view of a capacitor
38、, showing gate oxide surrounded by field oxide, with a poly “blanket“ making contact to the gate, and in turn being contacted by metal along two sides. It is assumed that there is also a low resistance contact to the substrate or well, at roughly the same positions as the polysilicon to metal contac
39、ts shown in the figure. It is fairly clear that when the tunneling current through the oxide becomes significant, there will be a voltage drop between the edge of the capacitor nearest to the metal lines and the center line. The symmetry of the structure implies that the voltage across the oxide wil
40、l be a minimum at the x = O line of this structure and will, of course, be a maximum at the metal electrode edges. EIA JESD35-3 95 3234600 O563233 68T W ADDENDUMNo. 1 Page 4 EWJESD35-1 - I I I I - - I I I I - Thin oxide edge Polysilicon edge I Poiysiticon to metai contact Figure 3.1 - Top view of a
41、MOS capacitor designed to minimize series resistance of width w. The x-y coordinate system shown is used in the analysis presented in the text. Note that the origin is on the center-line of the structure. Figure 3.2 shows the cross-section of an idealized version of the capacitor in figure 3.1. The
42、x = O line corresponds to the x = O line in figure 3.1. The substrate has been replaced by resistive material of conductivity us and thickness t,. It will become apparent later that the actual value of the quantities do not matter, as long as their product relates appropriately to the sheet resistan
43、ce of the substrate. This statement assumes that ts w, where w is the lateral dimension of the capacitor. The relationship between us, t, and the sheet resistance however, higher temperatures will decrease measured values. 3.5 Parasitics In designing and testing oxide test structures three sources o
44、f parasitic errors should be considered: 1) surface leakage, 2) isolation leakage and 3) parallel capacitance. Each will be dealt with in turn, but the leakage parasitics are the most likely to be of concern for wafer level ramp to breakdown testing. 1) Surface leakage: Surface leakage can appear as
45、 a low value resistive path between probe pads of an oxide test structure. The actual location of the leakage varies with the design. It may be directly between the probe pads, between the metal lines leading to the test structure or even between connections made to the test structure. Ordinarily it
46、 is not a significant problem provided that : a) the Fowler-Nordheim currents are larger than the ohmic surface leakage currents, b) the passivation, if it is present, helps to limit surface Ieakage and c) the testing is performed at reasonably low humidity. These conditions are not always fulfilled
47、. In the case of a difficult situation, guard rings should be considered in the design of the structures (see figure 6.1 in the Example Test Structure Section). These rings must be driven to the same potential as the line being guarded. This is typically done by a separate line driven by an operatio
48、nal amplifier that senses the measured line through a very high impedance input. If this system is adopted, the probe themselves are not guarded; however, an individual probe can be used to connect the output of the operational amplifier to the guard ring pads. 2) Isolation leakage: This is usually
49、an even smaller issue than surface leakage as the conduction is through a thick insulating dielectric. Still, defects in such insulators can lead to significant current flow. Short connections to test structures will minimize this issue as well as limiting the next parasitic issue, parallel capacitance. - EIA JESD35-L 75 3234600 0563237 225 ADDENDUMNo. 1 Page 8 EWJESD35-I 3) Parallel capacitance: Pardel or parasitic capacitance should not affect the dc breakdown of oxide test structures as long as the total RC of the system is much less than the ram
