1、JEDECSTANDARDTest Boards for Through-HolePerimeter Leaded Package ThermalMeasurementsJESD51-10JULY 2000JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subseque
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10、4or call (703) 907-7559JEDEC Standard No. 51-10-i-TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADEDPACKAGE THERMAL MEASUREMENTSCONTENTSPageForeword ii1 Scope 12 Normative references 13 Stock material 24 Board outline 35 Trace design 45.1 Top trace layer layout (both 1s and 2s2p PCBs) 45.2 Trace widths f
11、or 1s and 2s2p PCBs 65.3 Plated through-hole vias 65.4 Thermal pins (2s2p only) 75.5 Trace layers and connection routing 75.6 Buried layer layout (2s2p PCB only) 75.7 PCB metalization characteristics for 1s and 2s2p PCBs 85.8 Solder masks for 1s and 2s2p PCBs 86 Hand wiring 87 Data presentation 10Ta
12、bles1 PCB sizes for packages 32 PCB buried plane sizes 73 Wire size current limits 84 Specified parameters and values used 10Figures1a Cross section of 1s PCB showing trace and dielectric thicknesses in package placement 2and trace fan-out regions1b Cross section of 2s2p PCB showing trace and dielec
13、tric thicknesses 22 Example test board outer dimensions and edge connector design 33 Traces flared to perimeter 25 mm from package body 44 Nested design with traces flared to perimeter 25 mm from largest package body 55 Traces flared to perimeter 25 mm form SIP body 56 Hand wiring test board suggest
14、ion 9JEDEC Standard No. 51-10-ii-Foreword The measurement of the junction-to-ambient (RJA) thermal characteristics of an integrated circuit (IC)has historically been carried out using a number of test fixturing methods. The most prominent method isthe soldering of the packaged devices to a printed c
15、ircuit board (PCB). The characteristics of the testPCBs can have a dramatic (60%) impact on the measured RJA. Due to this wide variability, it isdesirable to have an industry-wide standard for the design of PCB test boards to minimize discrepanciesin measured values between companies.To obtain consi
16、stent measurements of RJAfrom one company to the next, the test PCB geometry andtrace layout must be completely specified for each package geometry tested. Such a completespecification would limit the flexibility of user companies who would like to design test boards for theirindividual needs. Thus,
17、 one characteristic of a test board specification is to allow some variability ofPCB test board design while minimizing measurement variability.This specification is intended for use with the thermal measurements and modeling specificationsgrouped under the JEDEC EIA/JESD51 series, 1. Specifically,
18、the electrical test procedures describedin JEDEC EIA/JESD51-1, “Integrated Circuit Thermal Measurement Method - Electrical Test Method(Single Semiconductor Device),” 2, EIA/JESD51-2, “Integrated Circuit Thermal Test MethodEnvironmental Conditions - Natural Convection (Still Air), 3, and EIA/JESD51-6
19、, “Integrated CircuitThermal Test Method Environmental Conditions - Forced Convection (Moving Air), 4.JEDEC Standard No. 51-10Page 1TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADEDPACKAGE THERMAL MEASUREMENTS(From JEDEC Board Ballot JCB-00-15, formulated under the cognizance of the JC-15.1 Subcommittee
20、on Thermal Characterization.)1ScopeThis specification covers through-hole mount perimeter leaded packages intended to be mounted on aPCB. It does not cover area array packages that require sockets or PGA packages.2 Normative references1 EIA/JESD51, Methodology for the Thermal Measurement of Componen
21、t Packages (Single Semiconductor Device).2 EIA/JESD51-1, Integrated Circuit Thermal Measurement Method - Electrical Test Method (Single Semiconductor Device).3 EIA/JESD51-2, Integrated Circuit Thermal Test Method Environmental Conditions -Natural Convection (Still Air).4 EIA/JESD51-6, Integrated Cir
22、cuit Thermal Test Method Environmental Conditions -Forced Convection (Moving Air).5 Electronics Engineers Handbook, 3rd Edition, Edited by D.G. Fink and D. Christiansen, McGraw-Hill Book Co., NY, 1989, p 6.166 MIL-W-5088L, Amdt. 1, Wiring, Aerospace Vehicle7 IPC-2222, Sectional Design Standard for R
23、igid Organic Printed Boards.8 IPC-2221, Generic Standard on Printed Board Design.JEDEC Standard No. 51-10Page 23 Stock materialThe PCB test board shall be made of FR-4 material. The finish size shall be 1.60 mm +/- 10% thick. Forhigh ambient or board temperature applications ( 125 C), use of other t
24、est board material is acceptableas long as the thermal conductivity of the material is reported and measurement correlations have beenestablished between the substitute material and FR-4.Trace thickness is achieved by starting with standard copper finished stock and then plating to finalthickness. A
25、 convention in PCB fabrication is to refer to copper thickness using the terminology ofounces of copper per square foot of board. An ounce of copper per square foot translates to a copperthickness of 35 m.The 1s test board has only a top trace layer in the component mounting and trace fan-out region
26、 (seefigure 1a). The copper trace thickness shall be 70 m (2 oz) +/- 20%. A bottom trace layer may be usedfor solder lands at the end of the fan-out traces and edge connection points. Connection to the edgeconnector outside the package fan-out region can be made with either the top or bottom signal
27、traces.The 2s2p version of this test board is formed by embedding two 35 m (1 oz) +0/-20% copper planes inthe PCB (as shown in figure 1b), while maintaining the finished thickness at 1.60 mm.Figure 1a Cross section of 1s PCB showing trace and dielectric thicknesses in packageplacement and trace fan-
28、out regionsFigure 1b Cross section of 2s2p PCB showing trace and dielectric thicknesses1.60 mmComponent Trace, 2 oz *Plane 1, 1 oz, solidPlane 2, 1 oz, solidBackside Trace, 2 oz *AA0.25 mm A 0.5 mm* = finished thickness:1 oz/ft2= 35 m2 oz/ft2= 70 m1.60 mmComponent Trace, 2 oz * = finished thickness:
29、2 oz/ft2= 70 mJEDEC Standard No. 51-10Page 34 Board outlineThe board shall be 101.5 mm x 114.5 mm +/- 0.25 mm in size for packages less than or equal to 40 mmon a side (see figure 2). A typical edge connector is depicted in figure 2. The edge connector can be pin-out and pitch modified for specific
30、needs. Multiple rows of vias along the edge connector are allowed.For various package sizes, refer to table 1 for the appropriate PCB size.Table 1 PCB sizes for packagesPackage Length PCB Size (+/- 0.25 mm)Pkg. Length 40 mm 101.5 mm x 114.5 mm (4.0“ x 4.5“)40 mm Pkg. Length 65 mm 127.0 mm x 139.5 mm
31、 (5.0” x 5.5”)65 mm Pkg. Length 90 mm 152.5 mm x 165.0 mm (6.0” x 6.5”)Figure 2 Example test board outer dimensions and edge connector design.JEDEC Standard No. 51-10Page 45 Trace design5.1 Top trace layer layout (both 1s and 2s2p PCBs)Traces should be laid out such that the test device will be cent
32、ered relative to a 101.5 mm x 101.5 mmsection towards the top of the board (away from the edge connector) for the smallest board. For largerboard sizes, locate the package at the top of the board in the center of a square whose length is the widthdimension of the board. The package shall be oriented
33、 such that the long dimension of the package bodyis perpendicular to the edge connector. The traces connecting to the package must extend at least 25 mmout from the edge of the device body. Trace lengths longer than this are allowed. Traces must be routedin a radial fashion (flared) to meet the edge
34、s of a rectangle such that the terminal via locations are equallyspaced over 90% of the perimeter of the sides of this rectangle. Traces must be flared out to the 25 mmperimeter adjacent to the side of the package on which they originate.Figure 3 Traces flared to perimeter 25 mm from package bodyA s
35、ingle PCB design can be used for a family of packages with the same pin pitch as long as the tracesare fanned out to meet the requirements for the largest body size (see figure 4).For packages with a single row of leads, the odd numbered pins should be fanned out to one side of thepattern and the ev
36、en numbered pins should fan out to the opposing side (see figure 5)JEDEC Standard No. 51-10Page 55 Trace design (contd)5.1 Top trace layer layout (both 1s and 2s2p PCBs) (contd)Figure 4 Nested design with traces flared to perimeter 25 mm from from largest packagebody.Figure 5 Traces flared to perime
37、ter 25 mm from SIP body.JEDEC Standard No. 51-10Page 65 Trace design (contd)5.2 Trace widths for 1s and 2s2p PCBsThe total trace widths connecting to one package terminal shall be 0.25 mm +/- 10%. Splitting of tracesin two parts, e.g. in order to keep force (power) and sense (measure) lines independ
38、ent, is allows as longas their summed widths meets the above specified total trace width. Achieving the finish size mayrequire some oversize in design to compensate for over-etching of the copper traces during processing.Traces should terminate in a plated through-hole for soldering interconnect pur
39、poses.5.3 Plated through-hole viasVias for Package Mounting: The finished (plated) diameter for all plated through-holes used for packagemounting shall be no less than the maximum pin diameter plus 0.15 mm and no more than the minimumpin diameter plus 0.60 mm 7. For rectangular pins, the diameter sh
40、all be calculated as equal to thediagonal of the rectangular cross-section of the lead. The via pad diameter shall nominal as specified inreference 8. The via pad diameter tolerance shall be +0.10/-0 mm.For example, for a DIP (JEDEC MO-001, Variation AJ) with the following dimensions:Min. lead width
41、: 0.381 mmMax. lead width: 0.584 mmNominal thickness: 0.25 mmThe lead diameters are as follows:Min. lead diameter: 0.46 mmMax. lead diameter: 0.64 mmThe plate through-hole vias are as follows:Min. finished hole diameter: 0.64 + 0.15 = 0.79 mm 7Max. finished hole diameter: 0.46 + 0.60 = 1.06 mm 7Via
42、pad diameter: 1.06 + 0.20 + 0.10 = 1.36 +0.10/-0 mm 8The drill hole diameter shall be such as to yield the finished hole diameters specified above. An isolationclearance region with a diameter at least 0.2 mm larger than the drill hole diameter shall exist in theburied solid planes around each plate
43、d through-hole via. Other than this isolation clearance area, theburied planes are to be unbroken. Some buried plane copper must exist between via isolation clearanceregions; the clearance regions are not to merge into one another. Except for any thermal pins (see 5.4),all package mounting vias shal
44、l be isolated from any buried solid planes.Trace fan-out vias: The plated through-hole vias at the border of the trace fan-out area and beyond shallhave a solder land of no less than 1.25 mm diameter with a drill hole of no less than 0.85 mm diameter.A block out area or isolation clearance of diamet
45、er no greater than 0.70 mm larger than the drill holediameter shall exist in the buried solid planes around each plated through-hole via. Other than thisisolation clearance area, the buried planes are to be unbroken. Some buried plane copper must existbetween via isolation clearance regions; the cle
46、arance regions are not to merge into one another.JEDEC Standard No. 51-10Page 75 Trace design (contd)5.4 Thermal pins (2s2p only)Pins that are directly connected to the die pad shall be connected to the top buried copper plane. Thesepins shall be isolated from the bottom copper plane as specified in
47、 5.3. A cross pattern on the connectedplane shall not be used; the plane shall remain unetched in the vicinity of the drill hole.5.5 Trace layers and connection routing1s PCB: The only pattern permitted within the flared perimeter (fan-out area) is the fan-out pattern andpackage footprint on the top
48、 trace layer. The bottom layer shall be used only for via termination andlimited connection routing to the edge connector. Routing to the edge connector is allowed in either thetop or bottom signal layers if the interconnection remains outside the flared perimeter of the through-holes. No traces are
49、 allowed to run under the PCB within the flared perimeter of the through-holes.Power connection routing should be designed to minimize voltage drops and self heating across the PCBtraces. Measurement force (power) and sense (measure) lines should be kept independent of each otherfrom the edge connector to the package terminals.2s2p PCB: The top trace layer shall be used for fan-out and interconnection to the edge connectoroutside the fan-out perimeter. Any required interconnection routing to the edge connector can be made
