1、EIA JESD53-3 96 W 3234600 0577364 728 W EINJEDEC STANDARD Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EINJESDS 1-3 AUGUST 1996 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT EIA JESD5L-3 96 m 3234600 0577Lb5 664 m NOTICE EWJEDEC Standards and Publication
2、s contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EM General Counsel. EINJEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings betwee
3、n manufacturers and purchases, facilitating interchangeability and Unprovernent of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of
4、JEDEC from manufacturing or seiiing products not codorming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or internationally. EINJEDEC Standards and Publications are ado
5、pted without regard to whether their adoption may involve patents or articles, materials, or processes. By such action, EWJEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the EWJEDEC Standards or hblications. The information incl
6、uded in EWJEDEC Standards and Publications represents a sound approach to product specification and application, principally fiom the solid state device manufacturer viewpoint. Within the EINJEDEC organization there are procedures whereby an EWJEDEC Standard or Publication may be uther processed and
7、 ultimately becomes an ANSEIA Standard. Inquiries, comments, and suggestions relative to the content of this EWJEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at ELA Headquarters, 2500 Wilson Boulevard, Arlington, VA 2220 1. Published by OELECTRONIC INDUSTRIES ASSO
8、CIATION 1996 Engineering Department 2500 Wilson Boulevard Arlington, VA 2220 1 TopyTight“ does not apply to JEDEC member companies as they are free to duplicate this document in accordance with the latest revision of the JEDEC Publication 2 1 “Manual of Organization and Procedure“. PRICE: Please ref
9、er to the current Catalog of EIA, JEDEC, and TIA STANDARDS and ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-7179) International (303-397-7956) Printed in U.S.A. All rights reserved EIA JESDSL-3 9b m 3234600 0577Lbb 5TO m EINJEDEC Standard 5 1-3 Page 1 Low
10、Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (From JEDEC Council Ballot JCB-95-40, formulated under the cognizance of JC-15.1 Committee on Thermal Characterization Techniques for Electronic Packages and Interconnects.) 1 Background 1.1 The measurement of the Junction-t
11、o-Ambient JA) thermal characteristics of an integrated circuit (IC) package has historically been carried out using a number of test fixturing methods. The most prominent fixturing method is the soldering of the packaged devices to a printed circuit board (PCB). The characteristics of the test PCBs
12、can have a dramatic (60%) impact on the measured 8jA. Due to this wide variability, it is desirable to have an industry wide standard for the design of PCB test boards to minimize discrepancies in measured values between companies. 1.2 To obtain consistent measurements of 8jA from one company to the
13、 next, the test PCB geometry and trace layout must be completely specified for each package geometry tested. Such a complete specification would limit the flexibility of user companies who would like to design test boards for their individual needs. Thus, one characteristic of a test board specifica
14、tion is to allow some variability of PCB test board design while minimizing measurement variability. 1.3 This specification should be used in conjunction with the electrical test procedures described in JEDEC Standard No. 5 1-1, “Integrated Circuit Thermal Measurement Method - Electrical Test Method
15、 (Single Semiconductor Device),” i, and JEDEC Standard No. 5 1-2, “Integrated Circuit Thermal Test Method Environmental Conditions - Natural Convection (Still Air),” 2. 1.4 References i JEDEC Standard No. 5 1-1, “Integrated Circuit Thermal Measurement Method - Electrical Test Method (Single Semicond
16、uctor Device).” 2 JEDEC Standard No. 5 1-2, “Integrated Circuit Thermal Test Method Environmental Conditions - Natural Convection (Still Air)., 3 Surface Mount Land Patterns (Configurations and Design Rules), Pub. No. ANSITPC-SM-782 (782A), Developed by the Institute for Interconnecting and Packagin
17、g Electronic Circuits, 1987. EIA JESD53-3 96 3234600 0577367 437 EWEDEC Standard 51-3 Page 2 4 “Electronics Engineers Handbook,“ 3rd Edition, Edited by D.G. Fink and D. Christiansen, McGraw-Hill Book Co., NY, 1989, p 6.16 5 MIL standard MIL-W-5088B 2 2.1 3 3.1 4 4.1 5 5.1 Scope This specification co
18、vers leaded surface mount components of lead pitch greater than 0.35 mm up to a body size of 48 mm. It is not intended for through-hole, ball grid array, or socketed components. See the appropriate test specifications for these package types. Purpose The purpose of this proposal is to describe param
19、eterized guidelines for thermal test board design with a “low“ effective thermal conductivity (1 signal layer in the trace fan-out area) compared to a multi-layer PCB which might include power and ground planes. The resulting test PCBs will show less than 10% PCB related variation in measured 8jA fo
20、r a given package geometry within the maximum and minimum range of all variable parameters. The specified parameters impact the area of the test board, the amount of copper traces (Cu) on the test board, and the resulting trace fan-out area, all important parameters to the heat sinking characteristi
21、cs of the PCB. It should be emphasized that values measured with these test boards cannot be used to directly predict any particular system application performance but are for the purposes of comparison between packages. Stock material The test PCB shall be made of FR-4 material. The material shall
22、be 1.57 mm (0.062“) +/- 10% thick. For high temperature applications, 125“C, use of other test board material is acceptable as long as the themal conductivity of the material is reported and measurement correlations have been established between the substitute material and FR-4. Board outline The bo
23、ard shall be 76.2 mm x 114.3 mm (3.0“ x 4.5“) +/- 0.25 mm (0.010“) in size for packages less than 27.0 mm (1.06“) on a side as shown in figure 1; or 101.6 mm x 114.3 mm (4.0“ x 4.5“) +/- 0.25 mm (0.010“) in size for packages with a maximum body length from 27.0 mm (1.06“) to 48.0 mm (1.9“) as shown
24、in figure 2. A typical edge connector is depicted in figure 1. The edge connector can be pin-out and pitch modified for company specific needs. Width modification of dimension F is allowed. Multiple rows of vias along the edge connector are allowed. EIA JESDSL-3 96 3234600 0577368 373 H=254 I E = 2.
25、387 mm D = 3.962 mm EWJEDEC Standard 51-3 Page 3 - y A 101.6 mm l I Bl14.3mm E = 2387 mm Dr3.962mm LA F=74.17mm I- Fr74.17mrn I Figure 1: PCB for packages 27 mm Figure 2: PCB for package a7 mm 6 Trace design: 6.1 Trace Layout: Traces should be laid out such that the test device will be centered rela
26、tive to a 76.2 mm x 76.2 mm (3.0“ x 3.0“) square in the section of the test board furthest removed from the edge connector for packages 27 mm and centered in a 101.6 mm x 101.6 mm (4.0“ x 4.0“) section for packages 127 mm. The traces connecting to the package must extend at least 25 mm out from the
27、edge of the device body. Trace lengths longer than this amount are allowed. For 4 sided packages, traces must be flared to meet the edges of a square such that the terminal via locations are equally spaced over 90% of the perimeter of the sides of this square adjacent to the leaded sides of the pack
28、age (figure 3). For packages with leads on 2 sides, traces may be flared or straight to meet plated through holes on 2.54 mm (O. 1“) centers (figure 4). For 4-sided designs, staggering of trace terminal soldering positions inward fiom the trace termination square is allowed to 2.54 mm (O. 1“) off th
29、e perimeter of the square (figure 5). For inline packages (2 sided designs), the length axis of the package must align with the length axis of the test PCB. For 2-sided designs, staggering of trace terminal soldering positions 2.54 mm (O. i“) inward fi-om the 25 mrn minimum trace length is allowed o
30、nly when the number of pins per side multiplied by 2.54 mm is greater than 75 mm for the smaller PCB and greater than 100 mm for the larger PCB. A trace design that nests packages with equal pin pitches on the same PCB is allowed as long as the above conditions are met (figure 5). EIA JESD53-3 7b 32
31、34b00 0577367 20T = EWJEDEC Standard 5 1-3 Page 4 6.2 Trace Widths: Trace widths shall be 0.254 mm (0.010“) wide +/-lo% at finish size for 0.5 mm or larger pin pitches. For finer pin pitches, the trace width shall be set to the lead width. Achieving the finish size may require some oversize in desig
32、n to compensate for over-etching of the Cu traces during processing. Traces should terminate in a plated through-hole for soldering interconnect purposes. See 6.8 for a description of the plated through-hole vias. Solder land patterns should conform to the package lead outlines as described in ANSI/
33、IpC publications 3 J. No solder lands should be designed in the nested configuration; instead, the traces in thesoldering region to the outer most lead tip of the largest package should be the same width as the lead before immediately necking down to 0.254 mm (0.010“). 6.3 Trace Layers: The package
34、fan-out trace layer will consist of traces on the top of the PCB oniy; bottom layer traces are not allowed within the fan-out region. t C = 25 mrn I 1-1 I ! 8 = 54.6 mm A EO 7 mm I T P t ? ? ? Figure 3: Traces flared to square 25 mm from package body 25 mm .- -.O I (38.1 rnm,38.1 mm) J i: v :I :i: :
35、i. v :.AL : :i: I. “ : “I. :i: u u :. v Figure 4: Traces flared to 2.54 mm centered vias 25 mm from package body EIA JESDSL-3 b m 3234600 0577170 T21 EINJEDEC Standard 5 1-3 Page 5 6.4 Connection Routing: Trace connection to the edge connector using either the top or bottom trace layers is allowed i
36、f the interconnection remains outside the flared perimeter (fan-out area) of the through holes (figure 6). No traces are allowed to run under the PCB inside the flared perimeter of the through holes. Measurement force (power) and sense (measure) lines should be independent of each other when routed
37、fiom the edge connector to the package pins. Figure 5: Nested PCB design (44-176PQFP) outside . Figure 6: Connection routing fan-out perimeter (optional) 6.5 Wiring to the Edge Connector: Manual wiring from the through holes to the edge connector shall be made with 22AWG copper wire (0.64 mm; 0.0254
38、“ diameter) or smaller if the connections are not designed as part of the trace pattern. Interconnect wiring to the edge connector shall be on the trailing edge of the board with respect to air flow direction and back side of the board with respect to the component placement. Interconnect wiring sha
39、ll be outside the fan-out area. Connection fiom the edge connector to the fan-out perimeter and fiom the fan-out perimeter to the power dissipation structures must be made in a four point method for force (power) and sense (measure) purposes. Wire and through hole diameters for heater force currents
40、 may need to be larger to accommodate high power tests. Use table 1 as a guide to determine the required wire diameter 4,5. EIA JESDSL-3 96 3234600 0577171 968 = 30 28 EWJEDEC Standard 5 1-3 Page 6 0.4 na 0.6 na Table 1 -Wire Size Current Limits 20 18 16 14 4.0 8.33 na 15.4 na 19.4 na 31.2 126 1 1.0
41、 I 24 I 1.6 I na I I 12 I na I40 I 6.6 PCB Metalkation Characteristics: Metaikation on the PCB should be 2 oz finished thickness after final processing (0.071 mm; 0.0028“). This is achieved by starting with a 1 oz Cu material and plating to 2 oz during PCB through hole plating process. This process
42、specification should be printed on ail drawings to insure proper processing. The thickness of the Cu tracks should be verified to +/- 20% aRer PCB fabrication since thickness variations greater than this can have an influence on the performance of the PCB . 6.7 Solder Masks: Solder masking is option
43、al. 6.8 Plated Through Hole Vias: The plated through hole vias should have a solder land diameter of no less than 1.27 mm (0.05“) with a drill hole of no less than 0.83 mm (O. 03 3 I). 7 Data presentation 7.1 Table 2 lists parameters specified by this document. The user column allows the user to inp
44、ut actual measured values from his test boards. 8 Board Thickness Board Dimension (pkg length 27 Board Dimension (27 mm ? pkg length 5 48 mm) m) EIA JESDSL-3 96 m 3234bOO 0577172 BT4 m 1.57 mm (0.062“) 76.2x114.3 mm (3.011x4.511) 101.6x114.3 mm (4.011x4.51) EINJEDEC Standard 5 1-3 Page 7 Via Drill Hole Wire Gauge (Sense) Wire Gauge (Heater Force) 0.83 mm (0.033“) 22AWG (0.64 mm; 0.0254“ diameter) EIA JESDSL-3 96 U 3234b00 05?3?3 730
