1、EIA/JEDECSTANDARDHigh Effective Thermal ConductivityTest Board for Leaded Surface MountPackagesJESD51-7FEBRUARY 1999ELECTRONIC INDUSTRIES ALLIANCEJEDEC Solid State Technology AssociationNOTICEEIA/JEDEC standards and publications contain material that has been prepared, reviewed, andapproved through
2、the JEDEC Board of Directors level and subsequently reviewed and approvedby the EIA General Counsel.EIA/JEDEC standards and publications are designed to serve the public interest througheliminating misunderstandings between manufacturers and purchasers, facilitatinginterchangeability and improvement
3、 of products, and assisting the purchaser in selecting andobtaining with minimum delay the proper product for use by those other than JEDEC members,whether the standard is to be used either domestically or internationally.EIA/JEDEC standards and publications are adopted without regard to whether or
4、not theiradoption may involve patents or articles, materials, or processes. By such action JEDEC does notassume any liability to any patent owner, nor does it assume any obligation whatever to partiesadopting the EIA/JEDEC standards or publications.The information included in EIA/JEDEC standards and
5、 publications represents a sound approachto product specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby an EIA/JEDECstandard or publication may be further processed and ultimately become an ANSI/EIA
6、standard.No claims to be in conformance with this standard may be made unless all requirements stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this EIA/JEDEC standard orpublication should be addressed to JEDEC Solid State Technology Association, 2500 Wil
7、sonBoulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.jedec.orgPublished byELECTRONIC INDUSTRIES ALLIANCE 1999Engineering Department2500 Wilson BoulevardArlington, VA 22201-3834“Copyright“ does not apply to JEDEC member companies as they arefree to duplicate this document in accordance w
8、ith the latest revision ofJEDEC Publication 21 “Manual of Organization and Procedure“.PRICE: Please refer to the currentCatalog of JEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179), International (303-397-7956)Printed in the U.S.A.All r
9、ights reservedPLEASE!DON”T VIOLATETHELAW!This document is copyrighted by the EIA and may not be reproduced withoutpermission.Organizations may obtain permission to reproduce a limited number of copiesthrough entering into a license agreement. For information, contact:Global Engineering Documents15 I
10、nverness Way EastEnglewood, CO 80112-5704 or callU.S.A. and Canada 1-800-854-7179, International (303) 397-7956JEDEC Standard No. 51-7Page 1HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FORLEADED SURFACE MOUNT PACKAGES(From JEDEC Board Ballot JCB-98-89, formulated under the cognizance of the JC-15.
11、1 Committee onThermal Characterization)1 BackgroundThe measurement of the junction-to-ambient (R JA ) thermal characteristics of an integrated circuit (IC)package has historically been carried out using a number of test fixturing methods. The most prominentfixturing method is the soldering of the pa
12、ckaged devices to a printed circuit board (PCB). Thecharacteristics of the test PCBs can have a dramatic (60%) impact on the measured R J A . Due to thiswide variability, it is desirable to have an industry-wide standard for the design of PCB test boards tominimize discrepancies in measured values b
13、etween companies.To obtain consistent measurements of R JA from one company to the next, the test PCB geometry and tracelayout must be completely specified for each package geometry tested. Such a complete specificationwould limit the flexibility of user companies who would like to design test board
14、s for their individual needs.Thus, one characteristic of a test board specification is to allow some variability of PCB test board designwhile minimizing measurement variability.Standard EIA/JESD 51-3, entitled “Low Effective Thermal Conductivity Test Board for Leaded SurfaceMount Packages,” 1, deta
15、ils design criteria related to the design of a single layer (1s) test PCB. Incontrast, this specification is dedicated to the design of a high effective thermal conductivity test PCB thatembodies two signal layers, a power plane, and a ground plane (2s2p PCB).This specification should be used in con
16、junction with the electrical test procedures described inJESD51-1, “Integrated Circuit Thermal Measurement Method - Electrical Test Method (SingleSemiconductor Device),” 2, and JESD51-2, “Integrated Circuit Thermal Test Method EnvironmentalConditions - Natural Convection (Still Air),” 3.1.1 Referenc
17、esEIA/JESD 51-3, “Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.”EIA/JESD 51-1, “Integrated Circuit Thermal Measurement Method - Electrical Test Method (SingleSemiconductor Device).”EIA/JESD 51-2, “Integrated Circuit Thermal Test Method Environmental Conditions - Na
18、turalConvection (Still Air).”ANSI/IPC-SM-782-1987, Surface Mount Land Patterns (Configurations and Design Rules).MIL standard MIL-W-5088BJEDEC Standard No. 51-7Page 22 ScopeThis specification covers leaded surface mount components. It is not intended for through-hole, ball gridarray, or socketed com
19、ponents. It does not cover packages with features (such as exposed die paddles)intended for direct thermal contact to multi-layer planes. See the appropriate test specifications for thesepackage types.3 PurposeThe purpose of this document is to describe parameterized guidelines for a thermal test bo
20、ard design with a“high” effective thermal conductivity compared to a single layer PCB. The resulting test PCBs areexpected to show less than 10% PCB-related variation in measured R JA for a given package geometrywithin the maximum and minimum range of all variable parameters. The specified parameter
21、s impact thearea of the test board, the amount of copper (Cu) traces on the test board, and the resulting trace fan-outarea, all of which are important parameters to the heat-sinking characteristics of the PCB.The high effective thermal conductivity test PCB gives a near best case thermal performanc
22、e valuecompared to the single layer low effective thermal conductivity PCB. It should be emphasized that valuesmeasured with these test boards cannot be used to directly predict any particular system applicationperformance.4 Stock MaterialThe test PCB shall be made of FR-4 material. The finished thi
23、ckness of the PCB shall be 1 .60 mm +/-10%. For high-temperature applications, 125 C, use of other test board material is acceptable as long asthe thermal conductivity of the material is reported and measurement correlations have been establishedbetween the substitute material and FR-4.Trace layers
24、and layer thicknesses are defined in figure 1 along with relative dielectric thicknesses betweenthe layers.Figure 1 Cross section of multi-layer PCB showing trace and dielectric thicknesses1.6 mmComponent Trace, 2 oz *Plane 1, 1 oz , solid *Plane 2, 1 oz , solid *Backside Trace, 2 oz * = finish thic
25、kness:1 oz/ft 2 = 0.0352 oz/ft 2 = 0.070 mmAA0.25 mm A 0.50 mmJEDEC Standard No. 51-7Page 35 Board Physical GeometriesThe PCB shall be 76.20 mm x 114.30 mm +/- 0.25 mm in size for packages with a maximum body lengthless than 27.0 mm on a side (figure 2); or 101.60 mm x 114.30 mm +/- 0.25 mm in size
26、for packages witha maximum body length from 27.0 mm to 48.0 mm (figure 3). A typical edge connector is depicted infigure 2. The edge connector may be pin-out and pitch modified for company specific needs. Widthmodification of dimension F is allowed.Figure 2 PCB for packages 27.0 mm long Figure 3 PCB
27、 for Package 27.0 mm long74.20 mm x 74.20 mm buried planes 99.60 mm x 99.60 mm buried planesB = 114.3 mmC = 9.53 mmD = 3.96 mmE = 2.39 mmF = 74.17 mmh = 1.981mmA = 101.6 mm1 mm1 mm99.6 mmB = 114.3 mmC = 9.53 mmD = 3.96 mmE = 2.39 mmF = 74.2 mmG = 1.98 mmH = 2.54 mmA = 76.2 mm1 mm1 mmJEDEC Standard N
28、o. 51-7Page 46 Component Side Trace Design6.1 Trace layoutTraces should be laid out such that the test device will be centered relative to a 76.20 mm x 76.20 mmsquare in the section of the test PCB furthest removed from the edge connector for packages 27.0 mm andcentered in a 101.60 mm x 101.60 mm s
29、ection for packages 27.0 mm. The traces connecting to thepackage must extend at least 25 mm out from the edge of the device body. Trace lengths longer than thisamount are allowed and must be noted in table 2. For packages with leads on four sides, traces must beflared to meet the edges of a square s
30、uch that the terminal via locations are equally spaced over 90% of theperimeter of the sides of this square adjacent to the leaded sides of the package (figure 4). For packageswith leads on 2 sides, traces may be flared or straight to meet plated-through holes on 2 .54 mm centers(figure 5). For inli
31、ne packages (2-sided designs), the length axis of the package must align with the lengthaxis of the test PCB. For 4-sided designs, staggering of trace terminal soldering positions inward from thetrace termination square is allowed to 2.54 mm off the perimeter of the square (figure 6). For 2-sideddes
32、igns, staggering of trace terminal soldering positions 2.54 mm inward from the 25 mm minimum tracelength is allowed only when the number of pins per side multiplied by 2.54 mm is greater than 75 mm forthe smaller PCB and greater than 100 mm for the larger PCB. A trace design that nests packages with
33、equal pin pitches on the same PCB is allowed as long as the above conditions are met (figure 6).Figure 4 Traces flared to square Figure 5 Traces flared to 2.54 mm25 mm from package body centered vias 25 mm from package body1A = 60.70 mmB = 54.60 mmC = 25 mm2.54 mm25 mm(38.1 mm,38.1 mm)JEDEC Standard
34、 No. 51-7Page 56 Component Side Trace Design (contd)6.2 Trace widthsTrace widths shall be 0 .25 mm wide +/-10% at finish size for 0.5 mm or larger pin pitches. For finer pinpitches, the trace width shall be equal to the lead width. Achieving the finish size may require someoversize in design to comp
35、ensate for over etching of the Cu traces during processing. Traces shouldterminate in a plated-through hole for soldering interconnect purposes. See 6.3 for a description of theplated-through hole vias. Solder land patterns should conform to the package lead outlines as described inANSI/IPC publicat
36、ions 4. No solder lands should be designed in the nested configuration; instead, thetraces in the soldering region to the outer most lead tip of the largest package should be the same width asthe lead before immediately necking down to 0.25 mm.6.3 Plated-through hole viasThe plated-through hole vias
37、 should have a solder land of no less than 1.25 mm diameter with a drill hole ofno less than 0.85 mm diameter. A block-out area or isolation clearance with a diameter no greater than0.70 mm larger than the drill hole diameter shall exist in the buried solid planes around each plated-throughhole via.
38、 Other than this isolation clearance area, the buried planes shall be unbroken. Some buried-planeCu must exist between via isolation clearance regions; the clearance regions must not merge into oneanother. No thermal vias shall be designed into the PCB.6.4 Metallization characteristicsMetallization
39、of the top and bottom trace layers on the PCB should be 2 oz (0.070 mm) finished thicknessafter final processing. This can be achieved by starting with a 1 oz Cu material and plating to 2 oz duringPCB through-hole plating process. This process specification should be printed on all drawings to ensur
40、eproper processing. The thickness of the Cu tracks should be verified to +/- 20% after PCB fabricationsince thickness variations greater than this can influence the performance of the PCB.JEDEC Standard No. 51-7Page 66 Component Side Trace Design (contd)Figure 6 Nested PCB design (44-176PQFP) Figure
41、 7 Power and Ground plane(dotted line shows possible routing) termination and routing possibilities7 Backside Trace DesignRouting connection between the through-hole vias described in 6.3 and the edge connector lands may bemade using the top or backside traces. Top layer interconnection must remain
42、outside the flared perimeter(fan-out area) of the through-holes. If hand wiring to the through-hole vias is selected instead, the backsidetrace design shall consist of only solder lands corresponding to the through-hole vias. Hand wiring shouldbe made following the specification of 7.1. All power tr
43、aces should be a minimum of 1 mm wide to handlepossible high currents. Measurement force (power) and sense (measure) lines should be independent ofeach other when routed from the edge connector to the package pins.1JC15 . 1 Therma l Test0 . 50mm P it ch44 PQFP Thru 1762 . 54 mm ref.2 . 54 mmr e f.Bu
44、ried PlaneRouting OptionsJEDEC Standard No. 51-7Page 77 Backside Trace Design (contd)7.1 Wiring to the edge connectorConnection (wiring) from the through-holes to the edge connector can be made with 22AWG copper wire(0 .65 mm diameter) or smaller if the connections are not designed as part of the tr
45、ace pattern. Interconnectwiring to the edge connector shall be on the trailing edge of the board with respect to air flow direction andback side of the board with respect to the component placement. Connection from the edge connector to thefan-out perimeter and from the fan-out perimeter to the powe
46、r dissipation structures must be made in afour-point method for force/power and sense/measure purposes. Wire and through-hole via diameters forheater force currents may need to be larger to accommodate high power tests. Use table 1 as a guide todetermine the required wire diameter 5,6.Table 1 Wire S
47、ize Current LimitsAWG Wire Size UL Current Capacity,(80 C), amperesMIL-W-5088Bamperes30 0.4 na28 0.6 na26 1.0 na24 1.6 na22 2.5 5.020 4.0 8.318 6.0 15.416 10.0 19.414 16.0 31.212 26.0 40.08 Power and Ground PlanesThe power and ground planes embedded in the board should be of 1 oz (0.035 mm thick) +0
48、/- 20% Cu.They must be unbroken except for via isolation clearance patterns. The power and ground planes shouldterminate 1.0 mm from the edges of the PCB. The power and ground planes should not be present in the9 .5 mm edge connector pattern location shown in figures 2 and 3.Power and ground connect
49、ion for the heater device on the IC can be made using the buried power andground planes. If so, ensure connection to the appropriate vias on the fan-out perimeter only.A via connection at the corners of each buried power and ground plane is allowed for power and groundwiring to vias at the ends of the fan-out traces as shown in figure 7. In addition, designed in traces nowider than 1 mm are allowed from the edge connector to the buried planes on the buried plane layers.9 Solder MasksSolder masking is optional.JEDEC Standard No. 51-7Page 810 Data
