1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD65BSEPTEMBER 2003JEDECSTANDARDDefinition of Skew Specificationsfor Standard Logic Devices(Revision of JESD65-A)NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subsequ
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9、ssociation 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 65BPage 1DEFINITIONS OF SKEW SPECIFICATIONS FOR STANDARD LOGIC DEVICES(From JEDEC Board Ballots JCB-02-67, JCB-02-112, JCB-02-113, and JCB-02-114, formulated under the cognizance of the JC-40 Co
10、mmittee on Digital Logic.)1 ScopeThis standard defines skew specifications and skew testing for standard logic devices.The purpose is to provide a standard for specifications to achieve uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by user
11、s.2 Terms and definitions These definitions are provided for the purpose of this document. For general definitions of skew time, see the latest revision of JEDEC Standard No. 99 Terms, Definitions, and Letter Symbols for Microelectronic Devices.2.1 Device terms and definitionsPLL device: A logic dev
12、ice that includes a phase-locked loop and may also include other logic functions, such as counters, registers, and buffers.2.2 Parameter terms and definitionsskew (time): The magnitude of the time difference between two events that ideally would occur simultaneously. controlled edge: The output sign
13、al edge that is locked to the PLL trigger reference. jitter: The time deviation of a PLL-generated controlled edge from its nominal position.threshold crossing: The point at which a logic signal transitions from one logic state to another.primary threshold crossing: The threshold crossing of a clock
14、 signal indicating the start of a new cycle and the end of the previous cycle.secondary threshold crossing: The threshold crossing of a clock signal indicating the second part of the clock cycle. JEDEC Standard No. 65BPage 23 Standard specificationsAll skew parameters are specified over the guarante
15、ed temperature and supply operating ranges. If more than one temperature or supply operating range is used, the range(s) for the skew specification(s) must be identified. PLL logic devices must be supplied with a stable input reference clock within the operating frequency range of the component.Tabl
16、e 1 Symbols for skew and other specifications NOTE 1 This parameter is not production tested. NOTE 2 The sample size shall be greater than or equal to 1000.NOTE 3 The sample size shall be greater than or equal to 2000.NOTE 4 The test load for this parameter may be a nonstandard load identified in th
17、e data sheet.Table 2 Example of suggested jitter specificationsNOTE 5 Test Loads and Conditions are shown in Clause 4 “Standard test circuits for skew testing” for the designated voltage range.NOTE 6 Operating frequency range is 10 MHz to 100 MHz.Symbol Parameter Units Notestsk(o)output skew ps, ns
18、1tsk(LH)output skew for low-to-high transitions ps, nstsk(HL)output skew for high-to-low transitions ps, nstsk(pr)process skew ps, nstsk(pp)part-to-part skew ps, nstsk(b)bank skew ps, ns 1tsk(p)pulse skew ps, nstsk(inv)inverting skew ps, ns 1, 4tsk()multiple-frequency skew ps, nst()static phase offs
19、et ps, nst()dyndynamic phase offset ps, nst()tottotal phase offset ps, nstjit(cc)cycle-to-cycle period jitter ps, ns 2, 5 tjit(per)period jitter ps, ns 2, 5tjit(hper)half-period jitter ps, nstjit(duty)duty cycle jitter ps, nstjit()phase jitter ps, ns 1, 3, 5lock (f) frequency lockedlock ()phase lock
20、edtLpower-up PLL lock time ns, mstL()PLL lock time after frequency change ns, mstrecL()PLL recovery after phase change ns, msnLcycles to acquire PLL lock cyclesODC PLL output duty cycle %Symbol Parameter Sample size Typ Max Unit Notestjit(cc)cycle-to-cycle period jitter 1,000 cycles x x ps 5, 6tjit(
21、per)period jitter 10,000 cycles x x ps 5, 6tjit()phase jitter 2,000 cycles x x ps 5, 6JEDEC Standard No. 65BPage 33 Standard specifications (contd)output skew (tsk(o): The skew between specified outputs of a single logic device with all driving inputs switching simultaneously and the outputs driving
22、 identical specified loads.An example of a multiple bank logic deviceAn example of a logic device without banksAn example of output waveformsOUTPUT 1INPUTOUTPUT 2OUTPUT 3OUTPUT 4OUTPUT 1INPUTOUTPUT 2OUTPUT 3OUTPUT 4INPUTOUTPUT 3OUTPUT 1tsk(o)tsk(o)VOHVOLVrefVOHVOLVrefVtest0 VVrefJEDEC Standard No. 6
23、5BPage 43 Standard specifications (contd)output skew (tsk(LH), tsk(HL): The skew between specified outputs of a single logic device when the outputs have identical specified loads and are switching in the same direction. NOTE Each input-to-output delay time is tested individually, and the difference
24、 is the skew.An example of a multiple bank logic deviceAn example of a logic device without banksAn example of output waveformsOUTPUT 1INPUT 1OUTPUT 2OUTPUT 3OUTPUT 4INPUT 3INPUT 2INPUT 4INPUTOUTPUT 3OUTPUT 1VOHVOLVrefVOHVOLVrefVtest0 VVreftsk(LH)=-tPLH(1)tPLH(3)tPHL(3)tPHL(1)tPLH(1) tPLH(3)tsk(HL)=
25、-tPHL(1) tPHL(3)OUTPUT 1INPUT 1INPUT 2OUTPUT 2OUTPUT 3OUTPUT 4JEDEC Standard No. 65BPage 53 Standard specifications (contd)process skew (tsk(pr): The magnitude of the difference in propagation delay times between corresponding terminals of two logic devices when both logic devices operate with the s
26、ame supply voltages, operate at the same temperature, and have identical package styles, identical specified loads, identical internal logic functions, and the same manufacturer.NOTE To calculate any other skew parameter between two logic devices, the process skew should be added to the selected ske
27、w parameter for a single logic device. EXAMPLE 1 Output skew between two logic devices = tsk(pr)+ tsk(o). EXAMPLE 2 Inverting skew between two logic devices = tsk(pr)+ tsk(inv).LOGIC DEVICE 1 LOGIC DEVICE 2An example of two logic devicesAn example of output waveformsOUTPUT 1OUTPUT 2OUTPUT 3OUTPUT 4I
28、NPUTOUTPUT 1OUTPUT 2OUTPUT 3OUTPUT 4INPUTINPUT, PART 1 & PART 2OUTPUT 1, PART 2OUTPUT 1, PART 1tsk(pr) tsk(pr)VOHVOLVrefVOHVOLVrefVtest0 VVrefJEDEC Standard No. 65BPage 63 Standard specifications (contd)part-to-part skew (tsk(pp): The magnitude of the difference in propagation delay times between an
29、y specified terminals of two logic devices when both logic devices operate with the same supply voltages, operate at the same temperature, and have identical package styles, identical specified loads, and identical internal logic functions.LOGIC DEVICE 1 LOGIC DEVICE 2An example of two partsAn examp
30、le of output waveformsOUTPUT 1OUTPUT 2OUTPUT 3OUTPUT 4INPUTOUTPUT 1OUTPUT 2OUTPUT 3OUTPUT 4INPUTINPUT, PART 1 & PART 2OUTPUT 3, PART 2OUTPUT 1, PART 1tsk(pp) tsk(pp)VOHVOLVrefVOHVOLVrefVtest0 VVrefJEDEC Standard No. 65BPage 73 Standard specifications (contd)bank skew (tsk(b): The output skew between
31、 outputs with a single driving input terminal.An example of a logic device with banksAn example of output waveformsOUTPUT 1OUTPUT 2OUTPUT 3OUTPUT 4INPUTINPUTBANK 1 OUTPUT 2BANK 1 OUTPUT 1tsk(b) tsk(b)VOHVOLVrefVOHVOLVrefVtest0 VVrefJEDEC Standard No. 65BPage 83 Standard specifications (contd)pulse s
32、kew (tsk(p): The magnitude of the time difference between the propagation delay times tPHLand tPLHwhen a single switching input causes one or more outputs to switch.An example of a logic deviceAn example of an output waveform and tsk(p)measurementINPUTOUTPUT 1VOHVOLVrefVtest0 VVreftPLHtPHLtsk(p) tPL
33、HtPHL=OUTPUT 1OUTPUT 2OUTPUT 3OUTPUT 4INPUTJEDEC Standard No. 65BPage 93 Standard specifications (contd)inverting skew (tsk(inv): The skew between specified outputs of a single logic device with all driving inputs connected together and the outputs switching in opposite directions while driving iden
34、tical specified loads.An example of a package with both inverting and non-inverting outputsAn example of output waveformsmultiple-frequency skew (tsk(): The skew between the controlled-edge position of two different output frequencies on a PLL or counting device that has more than one output frequen
35、cy, when both signals are rising or both signals are falling.NOTE If the multiple frequency skew specification includes combined rising and falling edges, this may be identified in a footnote.An example of an output waveformOUTPUT 1OUTPUT 2OUTPUT 3OUTPUT 4INPUTINPUTOUTPUT 3OUTPUT 1tsk(inv) tsk(inv)V
36、OHVOLVrefVOHVOLVrefVtest0 VVrefPLL OUTPUT FREQUENCY 2PLL OUTPUT FREQUENCY 1tsk()tsk()VOHVOLVrefVOHVOLVrefJEDEC Standard No. 65BPage 103 Standard specifications (contd)static phase offset (t(): The time interval between similar points on the waveforms of the averaged input reference clock and the ave
37、raged feedback input signal when the PLL is locked and the input reference frequency is stable.NOTE 1 PLL jitter may cause excursions of t()beyond the specified maximum.NOTE 2 The term “PLL reference zero delay” has been used for this concept but its use is deprecated.An example of input waveformsdy
38、namic phase offset (t()dyn): The incremental phase offset between the input reference clock and the feedback input signal of a PLL resulting from modulation of the input reference clock.total phase offset (t()TOT): The sum of static phase offset, dynamic phase offset, and phase jitter.cycle-to-cycle
39、 period jitter (tjit(cc): The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs.Examples of an output waveform and cycle-to-cycle period jitter measurementsNOTE In all these examples, the minimum value would be tcycle n = tcycle n+1, which is z
40、ero. Negative values are not possible.INPUT REFERENCE CLOCKFEEDBACK INPUTVOHVOLVrefVtest0 VVreft()()OUTPUTVOHVOLVreftcycle ntcycle n+1tjit(cc)= | tcycle n tcycle n+1| where tcycle nand tcycle n+1are any two adjacent cycles measured on controlled edges. tjit(cc+)= tcycle n+1 tcycle nwhere tcycle nand
41、 tcycle n+1are any two adjacent cycles measured on controlled edges, and the period of tcycle n+1 is longer than or equal to the period of tcycle n.tjit(cc)= tcycle n tcycle n+1where tcycle nand tcycle n+1are any two adjacent cycles measured on controlled edges, and the period of tcycle n is longer
42、than or equal to the period of tcycle n+1.JEDEC Standard No. 65BPage 113 Standard specifications (contd)period jitter (tjit(per): The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles.An example of an output waveform and jitter measurementhalf-period
43、 jitter (tjit(hper): The magnitude of the deviation in time duration between half cycle threshold crossings of a single over a random sample of half cycles.duty cycle jitter (tjit(duty): The magnitude of the deviation in time duration between the primary threshold crossing and the secondary threshol
44、d crossing in a cycle over a random sample of cycles.where fo is the nominal output frequency andtcycle nis any cycle within the sample measuredon controlled edgesIDEAL OUTPUTtcycle nVOHVOLVrefACTUAL OUTPUT1VOHVOLVreffotcycle ntjit(per) =1fothp(m)t jit(hper)= | t hp(m)- t hp(n)| where t hp(m) is the
45、 duration of any half cycle within the sample and t hp(n) is the duration of any other half cycle t hp(n)An example of half-period jitter12 foJEDEC Standard No. 65BPage 123 Standard specifications (contd)phase jitter (tjit(): The deviation in static phase offset t()for a controlled edge with respect
46、 to the mean value of t()in a random sample of cycles.An example of an output waveform and jitter measurementfrequency locked lock (f): The condition of a PLL device where the frequency of the feedback input is equal to the averaged reference input frequency within a designated tolerance.NOTE This d
47、efinition is useful in defining lock under conditions where the reference input is undergoing jitter or is skipping cycles.phase locked lock (): The condition of a PLL device where the reference input and the feedback input remain within the designated static phase offset.NOTE This definition requir
48、es the reference input to remain stable within a designated tolerance.power-up PLL lock time (tL): During PLL power up, the time required for the PLL to lock after achieving the minimum specified operating voltage.PLL lock time after frequency change (tL(): The time required for a PLL to lock after
49、the input reference clock frequency changes.NOTE The PLL lock time after frequency change is measured from the time the new input reference clock frequency is stable, to the time the PLL locks. PLL recovery time (trecL(): The time interval required for a PLL to recover phase lock after the input reference clock changes phase.cycles to acquire PLL lock (nL): The number of input clock cycles required for a PLL to lock when operating in the guaranteed operating range with a stable input reference clock freq
