1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD73-2AUGUST 2001JEDECSTANDARDStandard for Description of 3.3 V NFET Bus Switch Devices with Integrated Charge PumpsNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Council level and subs
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10、2201-3834 or call (703) 907-7559 JEDEC Standard No. 73-2Page 1STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS(From Board Ballot JCB-00-99, formulated under the cognizance of the JC-40 Committee on Digal Logic.)1 ScopeThis standard covers specifications for a fa
11、mily of 3.3 V NMOS FET bus switch devices with integrated charge pumps. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this standard is to provide a set of uniform data sheet parameters
12、for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices.2 Definitions for the purpose of this documentswitch device: A semiconductor logic device designed to connect
13、 or disconnect busses or control signals without active drivers in the connection path.connect: A state in a switch device characterized by a minimum series impedance through the designated electrical path.disconnect: A state in a switch device characterized by the high series impedance of the desig
14、nated electrical path.JEDEC Standard No. 73-2Page 23 Standard specifications3.1 Absolute maximum continuous ratings 1,2NOTE 1 Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may advers
15、ely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.NOTE 2 Under transient conditions these ratings may be exceeded as defined elsewhere in this specification.NOTE 3 The dc negative voltage ratings may be exceeded if the dc input clamp current r
16、atings are observed. 3.2 Recommended operating conditions3.3 Capacitance(1)NOTE 1 Capacitance is characterized but not testedSymbol Parameter Rating UnitsVDDSupply voltage -0.5 to 4.6 VVI dc input voltage, control terminals(3)-0.5 to 5.5 VVSW dc switch voltage(3)-0.5 to 5.5 VIIKdc input clamp -50 mA
17、IOKdc clamp current, switch terminals -50 mAISWdc continuous channel current 120 mATSTGStorage temperature -65 to 150 CSymbol Parameter Min Max UnitVDDSupply voltage 3.0 3.6 VVINControl input voltage 0 5.5 VVSWSwitch terminal voltage 0 5.5 VTAOperating free-air temperature -40 85CSymbol Parameter Co
18、ndition Typ. UnitCINControl input capacitance pFCSWSwitch terminal capacitance Switch disconnected pFJEDEC Standard No. 73-2Page 33 Standard specifications (contd)3.4 Power supply characteristicsNOTE 1 Per TTL driven control inputNOTE 2 All switch inputs grounded. One control pin toggling. All other
19、 control pins at VDDor GND.3.5 Switching characteristics over operating rangeNOTE 1 Path must be specified.NOTE 2 This parameter is not tested.NOTE 3 The maximum frequency at which the enable/select input can be continuously toggled without discharging the integrated charge pump. The channel frequen
20、cy has no influence on the charge pump.Symbol Description Test Conditions Max UnitIDDQuiescent power supply current VDD= 3.6 VVSW= GND or VDDmAIDDQuiescent power supply currentTTL control inputs high(1)VDD= 3.6 VVIN= 2.0 VVSW= GNDAQD Dynamic power supply current(2)VSW= GNDControl pin toggling at 10
21、MHz and 50% duty cycleA/MHzSymbol Description Min Typ Max UnittPLHtPHLData path propagation delay(1,2)nstPZHtPZLSwitch connect delay(1)nstPHZtPLZSwitch disconnect delay(1)nsfCNTL Control frequency(3)MHzJEDEC Standard No. 73-2Page 43 Standard specifications (contd)3.6 DC specificationsNOTE 1 See the
22、manufacturers data sheet. NOTE 2 The connect path must be specified. NOTE 3 Resistance is measured as V/I. For VSW= 0 V, the resistance is measured while VOUTis pulled higher to the designated current level. For VSW= 2.4 V, the resistance is measured while VOUTis pulled lower to the designated curre
23、nt level.NOTE 4 Not more than one output should be tested at a time. Duration of the test must not exceed one second. This is an optional parameter.NOTE 5 This is an optional parameter.NOTE 6 IOZis guaranteed with VSWbetween GND and 5.5V, but is tested at VSW= VDD.Symbol Parameter Test Conditions Mi
24、n Max UnitVIHHigh-level input voltage 2.0VVILLow-level input voltage0.8 VVPASSPass voltage (VO)VSW= 5.0 VVDD =3.3 VIout = -30 mA4.5VRON Switch connect resistance(2,3)VSW= 0 V ISW= (1)VSW=2.4 V ISW= (1)IOS Short circuit current(2,4)VSW= VDDVOUT= GNDmAIDDQuiescent power supply current VDD= Max., VIN=
25、VDDor GNDAVIKClamp diode voltage Switch TerminalsISW= -18 mAVControl Terminals,IIN= -18 mAVIOZCurrent during switch disconnect(6)VDD= Max.VSW= GND to 5.5 VVOUT= GNDAIILIIHControl input current VDD= Max. VI= GNDVI= VDDAIOFF Switch terminal leakage(5)VDD= 0 VVSW= 5.5 VJEDEC Standard No. 73-2Page 54 Te
26、st circuits and switching waveformsCL= 50 pF or equivalent (includes test setup and probe capacitance).RL= R1= 500 or equivalentRT= Pulse generator termination resistance Pulse generator has the following characteristics: tr 2.5 ns, tf= 2.5 ns, PRR 10 MHz4.1 Propagation delay measurementTest Switch
27、S1tPLHOpentPHLOpentPZHOpentPZL6.0 VtPHZOpentPLZ6.0 VDUTPulseGeneratorRTCLR1RL6.0 VOpenGNDSwitch InputSwitch OutputtPLHtPHL3.0 V1.5 V0 VVOHVOL1.5 VJEDEC Standard No. 73-2Page 64 Test circuits and switching waveforms (contd)4.2 Connect delay measurement4.2 Disconnect delay measurementNOTE Reference to
28、 Other Applicable JEDEC Standards and PublicationsControl InputSwitch OutputtPZHtPZL3.0 V1.5 V0 VVOHVOL1.5 VSwitch OutputVOHVOL1.5 V(Switch Input = GND)(Switch Input = 3.0 V)Control InputSwitch OutputtPLZtPHZ3.0 V1.5 V0 VVOHVOLSwitch OutputVOHVOL(Switch Input = GND)(Switch Input = 3.0 V)VOL + 0.3 VVOH - 0.3 V
