1、JEDEC STANDARD Ball Grid Array Pinouts Standardized for 16-Bit Logic Functions JESD75-2 JULY 2001 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Council level and subsequently reviewed
2、 and approved by the EIA General Counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and o
3、btaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials
4、, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specificatio
5、n and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an EIA standard. No claims to be in conformance with this standard may be made
6、unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org.
7、 Published by JEDEC Solid State Technology Association 200 i 2500 Wilson Boulevard Arlington, VA 2220 1-3834 This documentmay be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting m
8、aterial. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada (1-800-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved JEDEC Standard No. 75-2 Page 1 BALL GRID ARRAY PINOUTS STA
9、NDARDIZED FOR 16-BIT LOGIC FUNCTIONS (Formerly JEDEC Board Ballot JCB-00-104, formulated under the cognizance of the JC-40 Committee on Digital Logic.) 1 Scope This standard defines device pinout for 16-bit wide buffer, driver and transceiver functions. This pinout specifically applies to the conver
10、sion of DIP-packaged 16-bit logic devices to VFBGA-packaged 16-bit logic devices. To provide a pinout standard for 16-bit logic devices offered in a 56-ball area grid array package for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. 2 Def
11、initions for the purpose of this document DIP: Dual In-line Pin Package (gull-wing) VFBGA: Very-Thin-Profile Fine-Pitch Ball Grid Array (MO-225) SSOP: Shrink Small-Outline Package; 0.25“ lead pitch; 0.3“ wide body (MO-118) TSSOP: Thin Shrink Small-Outline Package; 0.5-mm lead pitch; 6.4-mm wide body
12、 (MO-153) TVSOP: Thin Very Small-Outline Package; 0.4-mm lead pitch; 4.4-mm wide body (MO-194) 3 Pinout standard 3.1 Description The following criteria shall be used to convert existing 16-bit logic device functions offered in 48- and 56- pin DIP packages (SSOP, TSSOP, TVSOP) to 16-bit logic device
13、functions offered in the 56-ball VFBGA package: A. Attributes for the VFBGA package shall be as follows: 56-Ball, 0.65-mm ball pitch with 4.5-mm x 7-mm body size and 6-row x 10-column ball matrix. B. Device conversion shall be as follows: 56-pin 56-ball C. The pinout conversions shall be in accordan
14、ce with the diagrams shown in section 3.3 and 3.6. JEDEC Standard No. 75-2 Page 2 3 Pinout standard (contd) 3.2 56-ball VFBGA (MO-225) TOP VIEW 0000000000 0000000000 0000 0000 0000 0000 0000000000 0000000000 ABCDEFGHJK Figure 1 - Pinout configuration 3.3 Pin conversion from 48-pin DIP to 56-ball VFB
15、GA The pin conversion adopts the naming convention of logic devices in 48-pin DIP packages (e.g., SSOP, TSSOP, TVSOP). Figure 2 - Pin conversion top view 3.4 Pin assignment for 56-ball VFBGA converted from 48-pin DIP ?GND Pins: B3, B4, D3, D4, G3, G4, J3, and J4 VDD Pins: C3, C4, H3, and H4 Control
16、Pins: Al, A6, K1, and K6 TU0 and Signal Pins: B1, B2, B5, B6, C1, C2, C5, C6, D1, D2, D5, D6, El, E2, E5, E6, F1, F2, F5, F6, G1, G2, G5, G6, H1, H2, H5, H6, J1, J2, J5, and J6 *No Connection Pins: A2, A3, A4, A5, K2, K3, K4, and K5 Unpopulated Locations: E3, E4, F3, and F4 JEDEC Standard No. 75-2 P
17、age 3 3 Pinout standard (contd) 3.5 56-ball VFBGA (MO-225) TOP VIEW I 0000000000 0000000000 O000 0000 O000 0000 0000000000 0000000000 ABCDEFGHJK Figure 3 - Pinout configuration 3.6 Pin conversion from 56-pin DIP to 56-ball VFBGA The pin conversion TSSOP, TVSOP). adopts the naming convention of logic
18、 devices in 56-pin DIP packages SSOP, Figure 4 - Pin conversion top view 3.7 Pin assignment for 56-ball VFBGA converted from 56-pin DIP ?GND Pins: B3, B4, D3, D4, G3, G4, J3, and J4 VDD Pins: C3, C4, H3, and H4 Control Pins: Al, A2, A3, A5, A6, K1, K2, K3, K5 and K6 TGND or Control Pins: A4, and K4
19、#U0 Pins: B1, B2, B5, B6, C1, C2, C5, C6, D1, D2, D5, D6, El, E2, E5, E6, F1, F2, F5, F6, G1, G2, G5, G6, H1, H2, H5, H6, J1, J2, J5, and J6 Unpopulated Locations: E3, E4, F3, and F4 JEDEC Standard No. 75-2 Page 4 4 Reference to other applicable JEDEC standards and publications JEP95, JEDEC Registered and Standard Outlines for Solid State and Related Products
