1、JEDEC I JESD75-3 STANDARD Ball Grid Array Pinouts Standardized for %Bit Logic Functions JULY 2001 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Council level and subsequently reviewed
2、 and approved by the EIA General Counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and o
3、btaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials
4、, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specificatio
5、n and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an EIA standard. No claims to be in conformance with this standard may be made
6、unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org.
7、 Published by JEDEC Solid State Technology Association 2001 2500 Wilson Boulevard Arlington, VA 22201-3834 This documentmay be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting mat
8、erial. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada (1-800-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIO
9、NS (Formerly JEDEC Board Ballot JCB-O 1-1 6, formulated under the cognizance of the JC-40 Committee on Digital Logic.) JEDEC Standard No. 75-3 Page 1 BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONS (Formerly JEDEC Board Ballot JCB-O 1-1 6, formulated under the cognizance of the JC-40
10、Committee on Digital Logic.) 1 Scope This standard defines device pinout for 8-bit wide buffer, driver, transceiver, latch and flip-flop functions. This pinout specifically applies to the conversion of DIP-packaged 8-bit logic devices to VFBGA-packaged 8-bit logic devices. The purpose of this standa
11、rd is to provide a pinout standard for 8-bit logic devices offered in a 20- ball area grid array package for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. 2 Definitions for the purpose of this document DIP: Dual In-line Pin Package (gul
12、l-wing) VFBGA: Very-Thin-Profile Fine-Pitch Ball Grid Array (MO-225, Variation BC) SSOP: Shrink Small-Outline Package; 0.65-mm lead pitch; 5.3-mm wide body (MO-150) TSSOP: Thin Shrink Small-Outline Package; 0.65-mm lead pitch; 4.4-mm wide body (MO-153) TVSOP: Thin Very Small-Outline Package; 0.4-mm
13、lead pitch; 4.4-mm wide body (MO-194) 3 Pinout standard 3.1 Description The following criteria shall be used to convert existing 8-bit logic device functions offered in 20- pin DIP packages (SSOP, TSSOP, TVSOP) to 8-bit logic device fwictions offered in the 20-ball VFBGA package: A. Attributes for t
14、he VFBGA package shall be as follows: 20-Ball, 0.65-mm ball pitch with 3-mm x 4-mm body size and 4-row x 5-column ball matrix. B. The pinout conversion shall be in accordance with the diagram shown in section 3.3. JEDEC Standard No. 75-3 Page 2 3 Pinout standard (contd) 3.2 20-ball VFBGA (MO-225 Var
15、iation BC) TOP VIEW ABCDE Figure 1 - Pinout configuration 3.3 Pin conversion from 20-pin DIP to 20-ball VFBGA The pin conversion adopts the naming convention of logic devices in 20-pin DIP packages (e.g., SSOP, TSSOP, TVSOP). 4 3 2 1 ABCDE Figure 2 - Pin conversion top view 3.4 Pin assignment for 20-ball VFBGA GND Pin: i VDD Pin: A3 Control Pins: A2, and A4 TU0 and Signal Pins: Al, B1, B2, B3, B4, C1, C2, C3, C4, D1, D2, D3, D4, E2, E3, and E4 4 Reference to other applicable JEDEC standards and publications JEP95, JEDEC Registered and Standard Outlines for Solid State and Related Products
