1、JEDECSTANDARDDescription of 1.8 V CMOS LogicDevicesJESD76APRIL 2000JEDEC Solid State Technology AssociationA Sector of theNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and app
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10、59JEDEC Standard No. 74Page 1DESCRIPTION OF 1.8 V CMOS LOGIC DEVICES(From JEDEC Board Ballot JCB-99-52, formulated under the cognizance of the JC-40 Committee onDigital Logic.)1 PurposeThe purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination ofconfusion
11、, ease of device specification, and ease of use.2 ScopeThis standard defines dc interface, switching parameters and test loading for digital logic devices basedon 1.8 V (nominal) power supply levels.3 Definitions for the purpose of this documentPrefixes “54” or “74” immediately preceding family name
12、 indicate the operating temperature range. Forexample, 54xxx refers to the Military (MIL) version of devices which are specified over temperaturerange of 55 C to +125 C. 74xxx refers to the Commercial (COML) version of devices which arespecified over 40 C to +85 C.4 Standard specifications4.1 Absolu
13、te maximum continuous ratings1,2SYMBOL PARAMETER CONDITIONS RATING UNITVDDdc Supply voltage -0.5 to +2.5 VVINdc Input voltage -0.5 to VDD+ 0.5 VVOUTdc Output voltage Output in OFF state -0.5 to VDD+ 0.5 VTSTGStorage temperature -65 to +150 CNOTES1 Absolute maximum continuous ratings are those values
14、 beyond which damage to the devicemay occur. Exposure to these conditions or conditions beyond those indicated may adverselyaffect device reliability. Functional operation under these conditions is not implied.2 Under transient conditions these ratings may be exceeded as defined elsewhere in thisspe
15、cification.4 Standard specifications (contd)4.2 Recommended operating conditionsLIMITSSYMBOL PARAMETERMIN MAXUNITVDDdc supply voltage 1.65 1.95 VVINInput voltage 0 VDDVVOUTOutput voltage 0 VDDVTAMBOperating free-air temperature -40 +85 C4.3 DC specificationsLIMITSSYMBOL PARAMETER TESTCONDITIONMIN MA
16、X UNITVIHInput High Voltage 0.65VDDVDD+ 0.3 VVILInput Low Voltage -0.3 0.35VDDVVOHOutput HighVoltageIOH= -100 A VDD 0.2 VVOHOutput HighVoltageIOH= -2 mA VDD 0.45 VVOLOutput Low Voltage IOL= 100 A 0.2 VVOLOutput Low Voltage IOL= 2 mA 0.45 VNOTES1 Over recommended operating conditions2 Voltages are re
17、ferenced to GNDMeasurement 2 Enable and disable times5 Test circuit and switching waveformsNOTES1 CLincludes probe, and jig capacitance.2 Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with inter
18、nal conditions such that the output is high except when disabled by the output control.3 All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr= tf 2 ns.4 The outputs are measured one at a time with one transition per measurement.5 tPLZand tPHZare t
19、he same as tdis.6 tPZLand tPZHare the same as ten.7 tPLHand tPHLare the same as tpd.VOL+ 0.15 VtPZHtPZLVDD/2VDD/2VDD/2VDD/2tPHZVOH 0.15 VOutput ControlOutput Waveform 1S1 at 2 x VDD(see note 2)Output Waveform 2S1 at GND(see note 2)tPLZtPLHtPHLVDD/2VDD/2VDD/2VDD/2InputOutputVDD0 VVOHVOLMeasurement 1
20、Propagation delay timesTEST S1tpdOpentPLZ/tPZL2 X VDDtPHZ/tPZHGNDOpenFrom OutputUnder TestCL= 30pF(see note 1)1k2 x VDDGNDS11k5 Test circuit and switching waveforms (contd)Measurement 3 Pulse duration (width)measurementstWVDD/2VDD/2InputVDD/2tsu thVDD/2VDD/2Timing InputData InputVDDVDD0 V0 VMeasurement 4 Setup and hold times
