1、JEDEC STANDARD Standard Description of 1.5 V CMOS Logic Devices JESD76-3 AUGUST 2001 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed a
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10、on, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 76-3 Page 1 STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES (From JEDEC Board Ballot JCB-01-34, formulated under the cognizance of the JC-40.1 Subcommittee on CMOS/BiCMOS Digital Logic.) 1 Scope This standard defines dc interface par
11、ameters and test loading for a CMOS digital-logic family based on 1.5 V (nominal) power supply levels and 1.5 V input tolerance. The purpose is to provide a standard for 1.5 V nominal supply voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device
12、 specification, and ease of use. 2 Definitions for the purpose of this document Prefixes: Prefixes ”54” or ”74” immediately preceding family name indicate the operating temperature range. For example, 54XXX refers to the Military (MIL) version of devices which are specified over the temperature rang
13、e of -55 C to 125 C. 74XXX refers to the Commercial (COML) version of devices that are specified over -40 C to 85 C. 3 Standard specifications 3.1 Absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (see Note 1): Supply voltage range, VDD . . . . . . . . . . .
14、 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 2.0 V Input voltage range, VI: Except I/O ports . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V I/O ports (see Note 1, 2) . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V Output voltage range, VO (see Note 1 and 2) .
15、. . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V Input clamp current, IIK (VI VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Voltage range applied to any output
16、in the high-impedance state or power - off state, VO (see Note 1 and 2) . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 C to 150 C NOTE 1 Stresses beyond those listed under “absolute maximum
17、ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum-rated conditions for extended periods
18、 may affect device reliability. NOTE 2 This value is limited to 2 V maximum. JEDEC Standard No. 76-3 Page 2 3 Standard specifications (contd) 3.2 Recommended operating conditions (see Note 3): MIN MAX UNIT Operating 1.4 1.6 VDD Supply voltage Data Retention Only (optional spec.) 1 V VIH High-level i
19、nput voltage VDD = 1.4 V to 1.6 V 0.65 VDD VDD + 0.3 V VIL Low-level input voltage VDD = 1.4 V to 1.6 V 0.3 0.35 VDD V VI Input voltage 0 VDD V VO Output voltage 0 VDD V ?t/?v Input transition rise or fall rate (see Note 4) 0 10 ns/V 54 Series 55 125 TA Operating free-air temperature 74 Series 40 85
20、 C NOTE 3 All unused inputs of the device must be held at VDD or GND to ensure proper device operation. NOTE 4 As measured between VIL(max) and VIH(min). 3.3 Electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Note 5): PARAMETER TEST CONDITI
21、ONS VDD MIN MAX UNIT IOH = 100 A 1.4 V 1.2 V VOH IOH = 2 mA VIH = 0.91 V, VIL = 0.49 V 1.4 V 0.75 VDD V IOL = 100 A 1.4 V 0.2 VOL IOL = 2 mA VIH = 0.91 V, VIL = 0.49 V 1.4 V 0.25 VDD V II VI = VDD to GND 1.6 V 10 A IOZ (see Note 6) VO = VDD to GND 1.6 V 10 A IDD VI = VDD or GND IO = 0 1.6 V 20 A NOT
22、E 5 VDD of the sending and receiving devices must track within 0.1 V to maintain adequate dc margins. NOTE 6 For I/O ports, the parameter IOZ includes the input leakage current. JEDEC Standard No. 76-3 Page 3 4 Test circuit and switching waveforms NOTE 1 CL includes probe, and jig capacitance. NOTE
23、2 Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. NOTE 3 All input pulses are supplied by generat
24、ors having the following characteristics: PRR = 10 MHz, ZO = 50 , tr = tf = 2 ns. NOTE 4 The outputs are measured one at a time with one transition per measurement. NOTE 5 tPLZ and tPHZ are the same as tdis. NOTE 6 tPZL and tPZH are the same as ten. NOTE 7 tPLH and tPHL are the same as tpd. From Out
25、put Under Test CL = 15pF (see note 1) MEASUREMENT 3. PULSE DURATION (WIDTH) MEASUREMENTS tW VDD/2 VDD/2 Input VDD/2 tsu th VDD/2 VDD/2 Timing Input Data Input VDD VDD 0 V 0 V MEASUREMENT 4. SETUP AND HOLD TIMES tPLH tPHL VDD/2 VDD/2 VDD/2 VDD/2 Input Output VDD 0 V VOH VOL MEASUREMENT 1. PROPAGATION
26、 DELAY TIMES MEASUREMENT 2. ENABLE AND DISABLE TIMES TEST S1 tpd Open tPLZ/tPZL 2 X VDD tPHZ/tPZH GND 2k 2k Open 2 x VDD GND S1 0 VVDD Output Control Input Output Waveform 2 S1 at GND (see note 2) Output Waveform 1 S1 at 2 x VDD (see note 2) VOL + 0.1 V tPZH tPZL VDD/2 VDD/2 VDD/2 VDD/2 tPHZ VOH 0.1 V tPLZ VDD 0 V JEDEC Standard No. 76-3 Page 4 6 Reference to other applicable JEDEC standards and publications JESD8-11, 1.5 V 0.1 V Power Supply Voltage and Interface Standard for Non-terminated Digital Intergrated Circuits, October 2000.
