1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD7932OCTOBER 2011JEDECSTANDARDAddendum No. 2 to JESD793 for 1.25 V DDR3U800, DDR3U1066,DDR3U1333, and DDR3U1600 NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level
2、and subsequently reviewed and approvedby the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchas
3、er in selecting and obtaining with minimumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoptionmay involve patents or ar
4、ticles, materials, or processes. By such action JEDEC does not assumeany liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach toproduct
5、 specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard orpublication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standard m
6、ay be made unless all requirements stated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC at the address below, or call (703) 9077559 orwww.jedec.orgPublished byJEDEC Solid State Technology Associa
7、tion 20113103 North 10th StreetSuite 240 SouthArlington, VA 222012107This document may be downloaded free of charge; however JEDEC retains thecopyright on this material. By downloading this file the individual agrees not tocharge for or resell the resulting material.PRICE: Please refer to www.jedec.
8、orgPrinted in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the JEDEC Solid State Technology Associationand may not be reproduced without permission.Organizations may obtain permission to reproduce a limited number of copies through entering into a license ag
9、reement. For information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240SArlington, Virginia 22201or call (703) 9077559JEDEC Standard No. 79-3-2Page 11.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600(From JEDEC Board Ballot, JCB-11-39, formulated under the c
10、ognizance of the JC-42.3 Subcommittee on Volatile RAM.)1 ScopeThe JESD79-3 document defines the DDR3 SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this addendum. The purpose of this addendum is
11、 to define the DDR3U specifications that supersede the DDR3 specifications in the JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 titles in JESD79-3 are to be interpreted as DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600, respectively, when applying towards DDR3U definition; un
12、less specifically stated otherwise.2 DDR3U VDD/VDDQ RequirementsDDR3U SDRAM is 1.5V endurant.DDR3U SDRAM operation at 1.5V is not supported.Table 1 Recommended DC Operating Conditions - DDR3U (1.25 V) operationSymbol Parameter/Condition Min Typ Max Units NotesVDD Supply voltage 1.19 1.25 1.31 V 1,2,
13、3,4VDDQ Supply voltage for Output 1.19 1.25 1.31 V 1,2,3,4NOTE 1 Maximum DC value may not be greater than 1.31 V. The DC value is the linear average of VDD/VDDQ(t) over a very long period of time (e.g., 1 sec).NOTE 2 If maximum limit is exceeded, input levels shall be governed by DDR3L specification
14、s depending on the value.NOTE 3 Under these supply voltages, the device operates to this DDR3U specifcation.NOTE 4 Once initialized for DDR3U operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation (see Figure 1).Table 2 Recommended DC
15、 Operating Conditions - DDR3L (1.35 V) operationSymbol Parameter/Condition Min Typ Max Units NotesVDD Supply voltage 1.283 1.35 1.45 V 1,2,3,4VDDQ Supply voltage for Output 1.283 1.35 1.45 V 1,2,3,4NOTE 1 Maximum DC value may not be greater than 1.425 V. The DC value is the linear average of VDD/VDD
16、Q(t) over a very long period of time (e.g., 1 sec).NOTE 2 If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.NOTE 3 Under these supply voltages, the device operates to this DDR3L specifcation.Once initialized for DDR3L operation, DDR3U operation may only be used if t
17、he device is in reset while VDD and VDDQ are changed for DDR3U operation (see Figure 1).JEDEC Standard No. 79-3-2Page 22 DDR3U VDD/VDDQ Requirements (contd)Figure 1 VDD/VDDQ Voltage Switch Between DDR3U and DDR3LTable 3 Absolute Maximum DC RatingsSymbol Parameter/Condition Rating Units NotesVDD Volt
18、age on VDD pin relative to Vss -0.4V 1.6V V 1,3VDDQ Voltage on VDDQ pin relative to Vss -0.4V 1.6V V 1,3VIN, VOUTVoltage on any pin relative to Vss -0.4V 1.6V V 1TSTG Storage Temperature -55 to +100oC1,2NOTE 1 Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent da
19、mage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
20、NOTE 2 Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.NOTE 3 VDD and VDDQ must be within 250 mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, when VDD and VDDQ are l
21、ess than 500 mV; VREF may be equal to or less than 300 mV.JEDEC Standard No. 79-3-2Page 33 1.25 V DDR3U AC and DC Logic Input Levels for Single-Ended Signals3.1 AC and DC Input Levels for Single-Ended Command and Address Signals3.2 AC and DC Input Levels for Single-Ended Data SignalsTable 4 Single-E
22、nded AC and DC Input Levels for Command and AddressSymbol ParameterDDR3U-800, DDR3U-1066DDR3U-1333, DDR3U-1600Unit NotesMin Max Min MaxVIH.CA(DC90) DC input logic high Vref + 0.090 VDD Vref + 0.090 VDD V 1VIL.CA(DC90) DC input logic low VSS Vref - 0.090 VSS Vref - 0.090 V 1VIH.CA(AC150) AC input log
23、ic high Vref + 0.150 Note 2 Vref + 0.150 Note 2 V 1, 2, 5VIL.CA(AC150) AC input logic low Note 2 Vref - 0.150 Note 2 Vref - 0.150 V 1, 2, 5VIH.CA(AC130) AC input logic high Vref + 0.130 Note 2 Vref + 0.130 Note 2 V 1, 2, 5VIL.CA(AC130) AC input logic low Note 2 Vref - 0.130 Note 2 Vref - 0.130 V 1,
24、2, 5VRefCA(DC)Reference Voltage for ADD, CMD inputs0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4NOTE 1 For input only pins except RESET#. Vref = VrefCA(DC).NOTE 2 See JESD79-3, 9.6 “Overshoot and Undershoot Specifications” (9.6.1).NOTE 3 The ac peak noise on VRefmay not allow VRefto deviate fro
25、m VRefDQ(DC)by more than +/-1% VDD (for reference: approx. +/- 12.5 mV). NOTE 4 For reference: approx. VDD/2 +/- 12.5 mV.NOTE 5 These levels apply for 1.25 V operation only. If the device is operated at 1.35 V the appropriate levels in JESD79-3-1, VIH/L.CA(DC90), VIH/L.CA(AC160), VIH/L.CA(AC135), et
26、c.) apply. The 1.35 V levels VIH/L.CA(DC90), VIH/L.CA(AC160), VIH/L.CA(AC135) etc.) do not apply when the device is operated in the 1.25 voltage range.Table 5 Single-Ended AC and DC Input Levels for DQ and DMSymbol ParameterDDR3U-800, DDR3U-1066 DDR3U-1333, DDR3U-1600Unit NotesMin MaxVIH.DQ(DC90) DC
27、 input logic high Vref + 0.090 VDD Vref + 0.090 VDD V 1VIL.DQ(DC90) DC input logic low VSS Vref - 0.090 VSS Vref - 0.090 V 1VIH.DQ(AC150) AC input logic high Vref + 0.150 Note 2 - - V 1, 2, 5VIL.DQ(AC150) AC input logic low Note 2 Vref - 0.150 - - V 1, 2, 5VIH.DQ(AC130) AC input logic high Vref + 0.
28、130 Note 2 Vref + 0.130 Note 2 V 1, 2, 5VIL.DQ(AC130) AC input logic low Note 2 Vref - 0.130 Note 2 Vref - 0.130 V 1, 2, 5VRefDQ(DC)Reference Voltage for DQ, DM inputs0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4NOTE 1 For input only pins except RESET#. Vref = VrefDQ(DC).NOTE 2 See JESD79-3, 9.
29、6 “Overshoot and Undershoot Specifications” (9.6.1).NOTE 3 The ac peak noise on VRefmay not allow VRefto deviate from VRefDQ(DC)by more than +/-1% VDD (for reference: approx. +/- 12.5 mV).NOTE 4 For reference: approx. VDD/2 +/- 12.5 mV.NOTE 5 These levels apply for 1.25 V operation only. If the devi
30、ce is operated at 1.35 V, the appropriate levels in JESD79-3-1 VIH/L.DQ(DC90), VIH/L.DQ (AC160), VIH/L.DQ(AC135), etc.) apply. The 1.35 V levels VIH/L.DQ(DC90), VIH/L.DQ(AC160), VIH/L.DQ(AC135), etc. ) do not apply when the device is operated in the 1.25 voltage range.JEDEC Standard No. 79-3-2Page 4
31、3.3 1.25 V DDR3U Electrical Characteristics and AC TimingTable 6 Timing Parameters by Speed Binaa. The setup and hold parameters in Table 6 apply for 1.25 V operation only. If the device is operated at 1.35 V, the respective pa-rameters in JESD79-3-1 ( tIS(base, AC160), tIS(base, AC135), tIH(base, D
32、C90), tDS(base, AC 160), tDS(base, AC135), tDH(base,DC90) etc.) apply. The 1.35 V setup/hold parameters ( tIS(base, AC160), tIS(base, AC135), tIH(base, DC90), tDS(base, AC160),tDS(base, AC135), tDH(base, DC 90) etc.) do not apply when the device is operated in the 1.25 voltage rangeParameter SymbolD
33、DR3U-800 DDR3U-1066 DDR3U-1333 DDR3U-1600Units NotesMin Max Min Max Min Max Min MaxData TimingData setup time to DQS, DQS# referenced to Vih.DQ(ac) / Vil.DQ(ac) levelstDS(base) AC150100 50 - - ps Refer to JESD79-3 d, 17Data hold time from DQS, DQS# referenced to Vih.DQ(dc) / Vil.DQ(dc) levelstDH(bas
34、e) DC90160 110 75 55 ps Refer to JESD79-3 d, 17Data setup time to DQS, DQS# referenced to Vih.DQ(ac) / Vil.DQ(ac) levelstDS(base) AC130145 110 60 40 ps Refer to JESD79-3 d, 17Command and Address TimingCommand and Address setup time to CK, CK# referenced to Vih.CA(ac) / Vil.CA(ac) levelstIS(base) AC1
35、50225 150 90 70 ps Refer to JESD79-3 b, 16Command and Address hold time from CK, CK# referenced to Vih.CA(dc) / Vil.CA(dc) levelstIH(base) DC90285 210 150 130 ps Refer to JESD79-3 b, 16Command and Address setup time to CK, CK# referenced to Vih.CA(ac) / Vil.CA(ac) levelstIS(base) AC130370 - 310 - 21
36、5 195 ps Refer to JESD79-3 b, 16, 27NOTE 1 The following general notes from page 20 apply to Table 6: NOTE 2 VDD =VDDQ = 1.25V + 0.06VJEDEC Standard No. 79-3-2Page 53.3 1.25 V DDR3U Electrical Characteristics and AC Timing (contd)Table 7 ADD/CMD Setup and Hold Base-Values for 1 V/ns 3.4 Address / Co
37、mmand Setup, Hold and DeratingTable 8 Derating values DDR3U-800/1066/1333/1600 tIS/tIH - ac/dc based AC150Unit ps DDR3U-800 DDR3U-1066 DDR3U-1333 DDR3U-1600 ReferencetIS(base) AC150 225 150 90 70 VIH/L.CA(ac)tIH(base) DC90 285 210 150 130 VIH/L.CA(dc)tIS(base) AC130 225+145 150+160 90+125 70+125 VIH
38、/L.CA(ac)NOTE (AC/DC referenced for 1 V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate)tIS, tIH derating in ps AC/DC basedAC150 Threshold - VIH(ac)=VREF(dc)+150mV, VIL(ac)=VREF(dc)-150mVCK,CK# Differential Slew Rate4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns
39、 1.0 V/nstIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIHCMD/ADD-Slew rate V/ns2.0 75 45 75 45 75 45 81 53 87 61 93 69 99 79 105 951.5 50 30 50 30 50 30 59 38 65 46 71 54 77 64 83 801.0 0 0 0 0 0 0 8 8 16 16 22 24 28 34 34 500.9 0 -3 0 -3 0 -3 8 5 16 13 24 21 30 31 36 470.8 -1 -8 -1 -
40、8 -1 -8 8 1 16 9 24 17 32 27 38 430.7 0 -13 0 -13 0 -13 8 -5 16 3 24 11 32 21 40 370.6 -1 -20 -1 -20 -1 -20 7 -12 15 -4 23 4 31 14 39 300.5 -10 -30 -10 -30 -10 -30 -2 -22 6 -14 14 -6 22 4 30 200.4 -25 -45 -25 -45 -25 -45 -12 -37 -9 -29 -1 -21 7 -11 15 5JEDEC Standard No. 79-3-2Page 63.4 Address / Co
41、mmand Setup, Hold and Derating (contd)Table 9 Derating values DDR3U-800/1066/1333/1600 tIS/tIH - AC/DC based AC130Table 10 Required time tVACabove VIH(ac) below VIL(ac) for valid transitionTable 11 Data Setup and Hold Base-Values tIS, tIH derating in ps AC/DC basedAlternate AC130 Threshold - VIH(ac)
42、=VREF(dc)+130mV, VIL(ac)=VREF(dc)-130mVCK,CK# Differential Slew Rate4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/nstIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIHCMD/ADD-slew rate V/ns2.0 65 45 65 45 65 45 71 53 77 61 83 69 89 79 95 951.5 44 30 44 30 44 30 53
43、38 59 46 65 54 71 64 76 801.0 0 0 0 0 0 0 8 8 16 16 22 24 28 34 34 500.9 3 -3 3 -3 3 -3 1 5 19132721333139470.8 5 -8 5 -8 5 -8 13 1 21 9 29 17 37 27 43 430.7 8 -13 8 -13 8 -13 16 -5 24 3 32 11 40 21 48 370.6 12 -20 12 -20 12 -20 20 -12 28 -4 36 4 44 14 52 300.5 10 -30 10 -30 10 -30 18 -22 26 -14 34
44、-6 42 4 50 200.4 5 -45 5 -45 5 -45 13 -37 21 -29 29 -21 37 -11 45 5Slew Rate V/ns tVAC 150mV ps tVAC 130mV psmin max min max 2.0 TBD - TBD -2.0 TBD - TBD -1.5 TBD - TBD -1.0 TBD - TBD -0.9 TBD - TBD -0.8 TBD - TBD -0.7 TBD - TBD -0.6 TBD - TBD -0.5 TBD - TBD -VIH(ac)=VREF(dc)+150mV, VIL(ac)=VREF(dc)
45、-150mVa.Cell contents shaded in red are defined as not supported.DQS, DQS# Differential Slew Rate4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/nstDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDHDQ Slew rate V/ns2.0 75 45 75 45 75 45 - - - - - - - - - -1.5 50 30 5
46、0 30 50 30 59 38 - - - - - - - -1.0 00000 0881616- - - - - -0.9 - - 0 -3 0 -3 8 5 16132421 - - - -0.8 - - - - -1 -8 8 1 16 9 24 17 32 27 - -0.7 - - - - - - 8 -516 3 241 322140370.6 - - - - - - - - 15 -4 23 4 31 14 39 300.5 - - - - - - - - - - 14 -6 22 4 30 200.4 - - - - - - - - - - - -7-115-5tDS, DH
47、 derating in ps AC/DC based aAlternate AC125 Threshold - VIH(ac)=VREF(dc)+125mV, VIL(ac)=VREF(dc)-125mVa.Cell contents shaded in red are defined as not supported.DQS, DQS# Differential Slew Rate4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/nstDS tDH tDS tDH tDS tDH tDS tDH tDS
48、 tDH tDS tDH tDS tDH tDS tDHDQSlewrateV/ns2.0 65 45 65 45 65 45 - - - - - - - - - -1.5 44 30 44 30 44 30 53 38 - - - - - - - -1.0 00000 0881616- - - - - -0.9 - - 3 -3 3 -3 11 5 19 13 27 21 - - - -0.8 - - - - 5 -8 13 1 21 9 29 17 37 27 - -0.7 - - - - - - 16 -5 24 3 32 11 40 21 48 370.6 - - - - - - -
49、- 28 -4 36 4 44 14 52 300.5 - - - - - - - - - - 34 -6 42 4 50 200.4 - - - - - - - - - - - -37-1455Slew Rate V/nsDDR3U-800/1066 (AC150) tVACpsDDR3U-800/1066/1333/1600 (AC130) tVACpsmin max min max 2.0 TBD - TBD -2.0 TBD - TBD -1.5 TBD - TBD -1.0 TBD - TBD -0.9 TBD - TBD -0.8 TBD - TBD -0.7 TBD - TBD -0.6 TBD - TBD -0.5 TBD - TBD -4.0 TBD - TBD -4.0 TBD - TBD -3.0 TBD - TBD -2.0 TBD - TBD -1.8 TBD - TBD -1.6 TBD - TBD -1.4 TB
