1、JEDEC STANDARD DDR4 SDRAM JESD79-4B (Revision of JESD79-4A, November 2013) JUNE 2017 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed a
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9、outh Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 79-4B -i- 1 Scope 1 2 DDR4 SDRAM Package Pinout and Addressing 2 2.1 DDR4 SDRAM Row for X4, X8 and X16.2 2.2 DDR4 SDRAM Ball Pitch .2 2.3 DDR4 SDRAM Columns for X4,X8 and X162
10、2.4 DDR4 SDRAM X4/8 Ballout using MO-207 2 2.5 DDR4 SDRAM X16 Ballout using MO-207 3 2.6 DDR4 SDRAM X32 Ballout using MO-XXX .4 2.7 Pinout Description6 2.8 DDR4 SDRAM Addressing.7 2.9 DDP Single Rank(SR) x16 from two x8 .9 3 Functional Description .11 3.1 Simplified State Diagram 11 3.2 Basic Functi
11、onality .12 3.3 RESET and Initialization Procedure.12 3.3.1 Power-up Initialization Sequence 12 3.3.2 VDD Slew rate at Power-up Initialization Sequence .13 3.3.3 Reset Initialization with Stable Power .14 3.4 Register Definition14 3.4.1 Programming the mode registers 14 3.5 Mode Register17 4 DDR4 SD
12、RAM Command Description and Operation .28 4.1 Command Truth Table28 4.2 CKE Truth Table.29 4.3 Burst Length, Type and Order30 4.3.1 BL8 Burst order with CRC Enabled .30 4.4 DLL-off Mode Clock to Data Strobe relationship . 92 4.24.1.2 READ Timing; Data Strobe to Data relationship . 93 4.24.1.3 tLZ(DQ
13、S), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation . 94 4.24.1.4 tRPRE Calculation 96 4.24.1.5 tRPST Calculation 97 4.24.2 READ Burst Operation . 98 4.24.3 Burst Read Operation followed by a Precharge . 109 4.24.4 Burst Read Operation with Read DBI (Data Bus Inversion) . 111 4.24.5 Burst Read Operation with
14、 Command/Address Parity 112 4.24.6 Read to Write with Write CRC 113 4.24.7 Read to Read with CS to CA Latency 114 4.25 Write Operation115 4.25.1 Write Timing Parameters .115 4.25.2 Write Data Mask 116 4.25.3 tWPRE Calculation 117 4.25.4 tWPST Calculation .118 4.25.5 Write Burst Operation 119 4.25.6
15、Read and Write Command Interval 134 4.25.7 Write Timing Violations . 135 4.25.7.1 Motivation 135 4.25.7.2 Data Setup and Hold Offset Violations 135 4.25.7.3 Strobe and Strobe to Clock Timing Violations . 135 4.26 Refresh Command . 135 4.27 Self refresh Operation 137 4.27.1 Low Power Auto Self Refres
16、h . 138 -ii-JEDEC Standard No. 79-4B - 4.27.2 Self Refresh Exit with No Operation command 139 4.28 Power down Mode. 140 4.28.1 Power-Down Entry and Exit 140 4.28.2 Power-Down clarifications 144 4.28.3 Power Down Entry and Exit timing during Command/Address Parity Mode is Enable 145 4.29 Maximum Powe
17、r Saving Mode 146 4.29.1 Maximum power saving mode 146 4.29.2 Mode entry 146 4.29.3 CKE transition during the mode 147 4.29.4 Mode exit 147 4.29.5 Timing parameter bin of Maximum Power Saving Mode for DDR4-1600/1866/2133/2400/2666/3200. 148 4.30 Connectivity Test Mode . 148 4.30.1 Introduction . 148
18、 4.30.2 Pin Mapping 148 4.30.3 Logic Equations 149 4.30.3.1 Min Term Equations . 149 4.30.3.2 Output equations for x16 devices 150 4.30.3.3 Output equations for x8 devices 150 40.30.3.4 Output equations for x4 devices 150 4.30.4 Input level and Timing Requirement . 151 4.30.5 Connectivity Test ( CT
19、) Mode Input Levels 152 4.30.5.1 Input Levels for RESET_n 153 4.30.5.2 Input Levels for ALERT_n . 153 4.31 CLK to Read DQS timing parameters . 154 4.32 Post Package Repair (hPPR) 156 4.32.1 Hard Fail Row Address Repair (WRA Case) 156 4.32.2 Hard Fail Row Address Repair (WR Case) . 157 4.32.3 Hard Fa
20、il Row Address Repair MR bits and timing diagram . 157 4.32.4 Programming hPPR & sPPR support in MPR0 page2 158 4.32.5 Required Timing Parameters 159 4.33 Soft Post Package Repair (sPPR). 159 4.33.1 Soft Repair of a Fail Row Address 160 5 On-Die Termination 161 5.1 ODT Mode Register and ODT State Ta
21、ble 161 5.2 Synchronous ODT Mode. 163 5.2.1 ODT Latency and Posted ODT . 164 5.2.2 Timing Parameters . 164 5.2.3 ODT during Reads. 166 5.3 Dynamic ODT 167 5.3.1 Functional Description 167 5.3.2 ODT Timing Diagrams 168 5.4 Asynchronous ODT mode . 169 5.5 ODT buffer disabled mode for Power down 170 5.
22、6 ODT Timing Definitions 171 5.6.1 Test Load for ODT Timings 171 5.6.2 ODT Timing Definitions . 174 6 Absolute Maximum Ratings 174 7 AC and DC Operating Conditions . 174 8 AC and DC Input Measurement Levels . 174 8.1 AC and DC Logic input levels for single-ended signals. 174 8.2 AC and DC Input Meas
23、urement Levels: VREF Tolerances. 175 8.3 AC and DC Logic Input Levels for Differential Signals 176 8.3.1 Differential signal definition . 176 8.3.2 Differential swing requirements for clock (CK_t - CK_c) . 176 8.3.3 Single-ended requirements for differential signals 177 8.3.4 Address, Command and Co
24、ntrol Overshoot and Undershoot specifications 178 8.3.5 Clock Overshoot and Undershoot Specifications . 179 8.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications 180 8.4 Slew Rate Definitions . 181 -iii-JEDEC Standard No. 79-4B -iv- 8.4.1 Slew Rate Definitions for Differential Input Si
25、gnals ( CK ) 181 8.4.2 Slew Rate Definition for Single-ended Input Signals ( CMD/ADD ) 182 8.5 Differential Input Cross Point Voltage 182 8.6 CMOS rail to rail Input Levels 183 8.6.1 CMOS rail to rail Input Levels for RESET_n . 183 8.7 AC and DC Logic Input Levels for DQS Signals 184 8.7.1 Different
26、ial signal definition . 184 8.7.2 Differential swing requirements for DQS (DQS_t - DQS_c) . 184 8.7.3 Peak voltage calculation method 185 8.7.4 Differential Input Cross Point Voltage . 186 8.7.5 Differential Input Slew Rate Definition 187 9 AC and DC output Measurement levels . 188 9.1 Output Driver
27、 DC Electrical Characteristics. 188 9.1.1 Alert_n output Drive Characteristic . 190 9.1.2 Output Driver Characteristic of Connectivity Test ( CT ) Mode . 191 9.2 Single-ended AC & DC Output Levels. 191 9.3 Differential AC & DC Output Levels. 192 9.4 Single-ended Output Slew Rate 192 9.5 Differential
28、 Output Slew Rate 193 9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode. 194 9.7 Test Load for Connectivity Test Mode Timing 194 10 Speed Bin 195 10.1 Speed Bin Table Note. 203 11 IDD and IDDQ Specification Parameters and Test conditions 204 11.1 IDD, IPP and IDDQ Measurement Conditio
29、ns 204 11.2 IDD Specifications. 219 12 Input/Output Capacitance 221 13 Electrical Characteristics and AC Timing 224 13.1 Reference Load for AC Timing and Output Slew Rate . 224 13.2 tREFI 224 13.3 Clock Specification . 225 13.3.1 Definition for tCK(abs) 225 13.3.2 Definition for tCK(avg) 225 13.3.3
30、Definition for tCH(avg) and tCL(avg) 225 13.3.4 Definition for tERR(nper) 225 13.4 Timing Parameters by Speed Grade 226 13.5 Rounding Algorithms 243 13.6 The DQ input receiver compliance mask for voltage and timing (see Figure 211) . 244 13.7 Command, Control, and Address Setup, Hold, and Derating .
31、 248 13.8 DDR4 Function Matrix 250JEDEC Standard No. 79-4BPage 1 1 Scope This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirement
32、s for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standards (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Each aspect of the changes for DDR4 SDRAM operation were considered and approved by com
33、mittee ballot(s). The accumulation of these ballots were then incorporated to prepare this JEDEC Standard, JESD79-4, replacing whole sections and incorporating the changes into Functional Description and Operation. DDR4 SDRAM STANDARD (From JEDEC Board Ballot JCB-16-56, formulated under the cognizan
34、ce of the JC-42.3 Subcommittee on DRAM Memories.)JEDEC Standard No. 79-4B Page 2 2 DDR4 SDRAM Package Pinout and Addressing 2.1 DDR4 SDRAM Row for X4, X8 and X16 The DDR4 SDRAM x4/x8 component will have 13 electrical rows of balls. Electrical is defined as rows that contain signal ball or power/ gro
35、und balls. There may be additional rows of inactive balls for mechanical support. The DDR4 SDRAM x16 component will have 16 electrical rows of balls. There may be additional rows of inactive balls for mechanical support. 2.2 DDR4 SDRAM Ball Pitch The DDR4 SDRAM component will use a ball pitch of 0.8
36、 mm by 0.8 mm. The number of depopulated columns is 3. 2.3 DDR4 SDRAM Columns for X4,X8 and X16 The DDR4 SDRAM x4/x8 and x16 component will have 6 electrical columns of balls in 2 sets of 3 columns. There will be columns between the electrical columns where there are no balls populated. The number o
37、f these columns is 3. Electrical is defined as columns that contain signal ball or power/ground balls. There may be additional columns of inactive balls for mechanical support. 2.4 DDR4 SDRAM X4/8 Ballout using MO-207 1 2 3 4 5 6 7 8 9 A VDD VSSQ TDQS_c 3 DM_n, DBI_n TDQS_t 2 , (NC) 1 VSSQ VSS A B V
38、PP VDDQ DQS_c DQ1 VDDQ ZQ B C VDDQ DQ0 DQS_t VDD VSS VDDQ C D VSSQ DQ4 (NC) 1 DQ2 DQ3 DQ5 (NC) 1 VSSQ D E VSS VDDQ DQ6 (NC) 1 DQ7 (NC) 1 VDDQ VSS E F VDD (C2) 5 ODT1 6 ODT CK_t CK_c VDD F G VSS (C0) 5 CKE1 6 CKE CS_n (C1) 5 (CS1_n) 6 TEN (NC) 7 G H VDD WE_n A14 ACT_n CAS_n A15 RAS_n A16 VSS H J VREF
39、CA BG0 A10 AP A12 BC_n BG1 VDD J K VSS BA0 A4 A3 BA1 VSS K L RESET_n A6 A0 A1 A5 ALERT_n L M VDD A8 A2 A9 A7 VPP M N VSS A11 PAR A17 (NC) 4 A13 VDD N NOTE 1 These pins are not connected for the X4 configuration. NOTE 2 TDQS_t is not valid for the x4 configuration. NOTE 3 TDQS_c is not valid for the
40、x4 configuration. NOTE 4 A17 is only defined for the x4 configuration. NOTE 5 These pins are for stacked component such as 3DS. For mono package, these pins are NC. NOTE 6 ODT1 / CKE1 /CS1_n are used together only for DDP. NOTE 7 TEN is optional for 8Gb and above. This pin is not connected if TEN is
41、 not supported.JEDEC Standard No. 79-4BPage 3 Figure 1 D D R4 Ball Assignments for the x4/8 component 2.5 DDR4 SDRAM X16 Ballout using MO-207 1 2 3 4 5 6 7 8 9 A VDDQ VSSQ DQU0 DQSU_c VSSQ VDDQ A B VPP VSS VDD DQSU_t DQU1 VDD B C VDDQ DQU4 DQU2 DQU3 DQU5 VSSQ C D VDD VSSQ DQU6 DQU7 VSSQ VDDQ D E VSS
42、 DMU_n/ DBIU_n VSSQ DML_n DBIL_n VSSQ VSS E F VSSQ VDDQ DQSL_c DQL1 VDDQ ZQ F G VDDQ DQL0 DQSL_t VDD VSS VDDQ G H VSSQ DQL4 DQL2 DQL3 DQL5 VSSQ H J VDD VDDQ DQL6 DQL7 VDDQ VDD J K VSS CKE ODT CK_t CK_c VSS K L VDD WE_n/ A14 ACT_n CS_n RAS_n/ A16 VDD L M VREFCA BG0 A10/ AP A12/ BC_n CAS_n/ A15 VSS M
43、N VSS BA0 A4 A3 BA1 TEN N P RESET_n A6 A0 A1 A5 ALERT_n P R VDD A8 A2 A9 A7 VPP R T VSS A11 PAR NC A13 VDD T 1234 89 567 A B C D E F G H J K L MO-207 Variation DT-z (x4) Populated ball Ball not populated N M 1234 89 567 A B C D E F G H J K L MO-207 Variation DW-z (x4) N M 10 11 P R T U V W Y AA AB AC with support balls
