1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD8-17NOVEMBER 2004JEDECSTANDARDDriver Specifications for 1.8 V Power Supply Point-to-Point Drivers NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Council level and subsequently revie
2、wed and approved by the EIA General Counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting an
3、d obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materi
4、als, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specifica
5、tion and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publicati
6、on should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2004 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charg
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8、erved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, conta
9、ct: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 8-17Page 1DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERSFrom JEDEC Board Ballot JCB-20-106 and JCB-02-107, formulated under the guidance of
10、 JC-16 Committe on Interface Technology 1 ScopeThis material is intended to be reflected in supplier specifications for point to point DDR devices ranging from 400 Mb/s to 800 Mb/s operation.It is a method to specify driver impedance with something other than a number that does not nec-essarily defi
11、ne how it operates in a real net This standard addresses this issue using net lengths and specifies how much uncertainty can exist in the data for each speed supported.The purpose of this standard is to provide a standard of specification for uniformity, multiplicity of sources, elimination of confu
12、sion and ease of device specification and design by users2 Standard specificationsTable 1 identifies the driver specifications for 1.8 V point-to-point devices.NOTE 1 A part may use either the tDQSQ method (strobe based) or the tAC method (clock based) NOTE 2 This test is not meant to be a productio
13、n test criteria. NOTE 3 Each design can be simulated for how much tAC/tDQSQ should grow and each die revision can and should be characterized into test net structures (terminated and un-terminated)NOTE 4 Only one DQ pin at a time is to be simulated/characterized (all other DQs quiet). NOTE 5 The gro
14、wth in tAC (or tDQSQ) is on a per edge basis. The total growth of uncertainty in the data eye is the sum of both the plus and minus value. Table 1 Driver specifications for 1.8V Point-to-Point devicesNominal Data RateNet Length(Class-X/ Class-Y)tACUn-Terminated tDQSQUn-TerminatedNotes400Mb/s 1250ps/
15、833ps tAC +/-150ps tDQSQ +/-150ps 1.2,3,4,5600Mb/s 833ps/556ps tAC +/-125ps tDQSQ +/-125ps 1,2,3,4,5800Mb/s 625ps/417ps tAC +/-100ps tDQSQ +/-100ps 1,2,3,4,5JEDEC Standard No. 8-17Page 23 Outline of jitter modulation test test method for point-to-point devices Attach a driver to an un-terminated tra
16、nsmission line, of 0.5X the resonance length for Class-X and 0.33X resonance length for Class-Y. Assert a constant frequency signal onto the line, consistent with data rate of the device. Measure jitter at far-end of the transmission line using input clock as reference (effectively tAC). NOTE Jitter
17、 is measured at Vddq/2 and not at crosspoint. The bit pattern in Figure 1 must be used. Next perform the same test but into a terminated transmission line. Compare the results of the two situations. The standard specification is a limit on how much the tAC envelope can grow from the terminatedcase t
18、o the un-terminated case. Alternately, the growth in tDQSQ could be characterized insteadof tAC. The un-terminated case is meant to represent real application conditions. The amount ofgrowth can be simulated and characterized in this fashion and should be due only to net effects,driver characteristi
19、cs, and inter-symbol interference. Figure 1 Bit patternTo eliminate system board effects, only one driver at a time is to be characterized in such afashion. Since application requirements vary significantly, a target driver impedance andassociated application range of net impedances must be chosen f
20、rom the table below andidentified with the component. More than one range can be supported through various means, buta minimum of one range must be supported. Other DQs Data Pattern for DQ Under Test 0000 00000101010011001100110001110001110001110101JEDEC Standard No. 8-17Page 33 Outline of jitter mo
21、dulation test test method for point-to-point devices (contd)NOTE 1 A device compliant with the point to point specification must support at least one of the driver impedance values across its associated net impedance range. NOTE 2 The device must support either class-X and class-Y net topologies (fo
22、r class-X devices) or class-Y net topologies (for class-Y devices).NOTE 3 Timing values are guaranteed by design and characterization against open-ended (no load) net structures. Performance in real applications will vary as a result of true loading conditions. Device verification against real appli
23、cation conditions is the responsibility of the consumer. NOTE 4 A device may support more than one impedance value through the use of variable impedance (or impedance adjustment). However, such functionality is not required.Table 2 Driver Impedance ValuesDriver Impedance(s) SupportedTarget Net Imped
24、anceNet Impedance Range Notes30 ohms 30 ohms 27 - 33 ohms 1,2,3,440 ohms 40 ohms 36 - 44 ohms 1,2,3,450 ohms 50 ohms 45 - 55 ohms 1,2,3,460 ohms 60 ohms 54 - 66 ohms 1,2,3,480 ohms 80 ohms 72 - 88 ohms 1,2,3,4“X” ohms “X” ohms X +/- 10% ohms 1,2,3,4JEDEC Standard No. 8-17Page 4This page intentionall
25、y left blank.Rev. 9/02 Standard Improvement Form JEDEC JESD8-17 The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collec
26、ted and dispersed to the appropriate committee(s). If you can provide input, please complete this form (it can be edited in Acrobat Exchange) and return to: JEDEC Attn: Publications Department 2500 Wilson Blvd. Suite 220 Arlington, VA 22201-3834 Fax: 703.907.7583 1. I recommend changes to the follow
27、ing: Requirement, paragraph number Test method number Paragraph number The referenced paragraph number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date:
