1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD826SEPTEMBER 2011JEDECSTANDARD1.2 V HIGHSPEED LVCMOS (HS_LVCMOS) INTERFACE NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and approv
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3、inimumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoptionmay involve patents or articles, materials, or processes. By
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8、rds and Publications online athttp:/www.jedec.org/Catalog/catalog.cfmPrinted in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the JEDEC Solid State Technology Associationand may not be reproduced without permission.Organizations may obtain permission to repro
9、duce a limited number of copies through entering into a license agreement. For information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240SArlington, Virginia 22201or call (703) 9077559JEDEC Standard No. 8-26Page 11.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE(From
10、JEDEC Board Ballot JCB-11-48, formulated under the cognizance of the JC-16 Committee on Interface Technology.)1 ScopeThis standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-termi
11、nated interface has a switching range that is nominally expected to be 0 V to 1.2 V and is primarily intended to support communications with Wide I/O SDRAM devices.2 1.2 V High-speed LVCMOS (HS_LVCMOS) interface specifications2.1 Recommended DC operating conditionsTable 1 Recommended DC operating co
12、nditionsMin. Typ. Max. UnitVDD 1.14 1.20 1.30 V Input Buffer PowerVDDQ 1.14 1.20 1.30 V I/O Buffer Power2.2 Input levelTable 2 Input levelParameter Symbol Min Max UnitInput high level (AC) VIH(AC) 0.80*VDD(or VDDQ) VDD(or VDDQ)+0.2 VInput low level (AC) VIL(AC) -0.2 0.20*VDD(or VDDQ) VInput high lev
13、el (DC) VIH(DC) 0.70*VDD(or VDDQ) VDD(or VDDQ)+0.2 VInput low level (DC) VIL(DC) -0.2 0.30*VDD(or VDDQ) V= Dont CareVIH(AC)VIL(AC)VIH(DC)VIL(DC)InputNote: AC level is guaranteed transition point.DC level is hysteresis.LevelFigure 1 Input AC timing definitionJEDEC Standard No. 8-26Page 22.3 Output me
14、asurement levelTable 3 Output measurement LevelParameter Symbol Min Max UnitOutput high voltage VOH 0.80 * VDDQ - VOutput low voltage VOL - 0.20 * VDDQ V2.4 AC input over/undershootTable 4 AC input over/undershoot Parameter SpecificationMaximum peak amplitude allowed for overshoot area 0.35 VMaximum
15、 peak amplitude allowed for undershoot area 0.35 VMaximum overshoot area above VDD/VDDQ 0.8 V-nsMaximum undershoot area below VSS/VSSQ 0.8 V-nsOvershoot AreaMaximum AmplitudeVDDUndershoot AreaMaximum AmplitudeVSSVolts(V)Time (ns)Figure 2 AC overshoot and undershoot definition for input pinsRev. 9/02
16、 Standard Improvement Form JEDEC The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the approp
17、riate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 Fax: 703.907.7583 1. I recommend changes to the following: Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date:
