1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-16AMAY 2007JEDECSTANDARDDefinition of the SSTUA32866 1.8 V Configurable Registered Buffer withParity Test for DDR2 RDIMMApplications(Revision of JESD82-16, November 2005)NOTICE JEDEC standards and publications contain material that has been prepared, re
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5、s and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and sugge
6、stions relative to the content of this JEDEC standard or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arling
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8、blications at www.jedec.org Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies t
9、hrough entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-16APage 1DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFERWITH PARITY FOR DDR
10、2 RDIMM APPLICATIONS(From JEDEC Board Ballot JCB-05-101 and JCB-07-10, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 reg
11、istered buffer with parity test for DDR2 RDIMM applications.The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.NOTE The designation SSTUA32866 refers to the
12、part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.2 Device standard2.1 DescriptionThis 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with par
13、ity is designed for 1.7 V to 1.9 V VDDoperation.All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18 specifications
14、. The error (QERR) output is 1.8 V open-drain driver.The SSTUA32866 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.The SSTUA32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with
15、 the data received on the DIMM-independent D-inputs (D2D3, D5D6, D8D25 when C0 = 0 and C1 = 0; D2D3, D5D6, D8D14 when C0 = 0 and C1=1; or D1D6, D8D13 when C0 = 1 and C1=1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even parity, i.e.,
16、valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known logic state.When used as a single device, the C0 and C1 inputs are tied low. In this configurati
17、on, parity is checked on the PAR_IN input which arrives one cycle after the input data to which it applies. Two cycles after the data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.JEDEC Standard No. 82-16APage 22 Device standard (contd)2.1 Description (con
18、td)When used in pairs, the C0 input of the first register is tied low and the C0 input of the second register is tied high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the first device. Two
19、clock cycles after the data are registered the corresponding PPO and QERR signals are produced on the second device. The PPO output of the first register is cascaded to the PAR_IN of the second register. The QERR output of the first register is left floating and the valid error information is latche
20、d on the QERR output of the second register.If an error occurs and the QERR output is driven low, it stays latched low for two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched as low for a clock duration equal to the
21、 parity-error duration or until RESET is driven low. For the case where a parity error occurs just before the device enters the low-power mode (LPM), see Table 4, Figure 18, Figure 19, and Figure 20. The DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are not included in the parity check computati
22、on. The parity error output QERR will be reset to high by RESET transitioning low and will not be decoded until after RESET goes high and DCS and/or CSR are asserted low.The C0 input controls the pinout configuration for the 1:2 pinout from A configuration (when low) to B configuration (when high).
23、The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the
24、 register will be cleared and the Qn outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data
25、inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SSTUA32866 must ensure that the outputs will remain low, thus ensuring no glitches on the output. If the data inputs are not held low, then
26、DCS and CSR must be held high, DODT and DCKE must be held low, and all other inputs must remain stable (either low or high) for a minimum of tACT(max) after the rising edge of RESET. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low st
27、ate during power up.The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forc
28、ed low. The LVCMOS RESET, C0, and C1 inputs must always be held at a valid logic high or low level.The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states when both DCS and CSR inputs are
29、 high. If either DCS or CSR input is low, the Qn and PPO outputs will function normally. The RESET input has priority over the DCS and CSR control and when driven low will force the Qn and PPO outputs low, and the QERR output high. If the DCS control functionality is not desired, then the CSR input
30、can be hard-wired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. To control the low-power mode with DCS only, then the CSR input should be pulled JEDEC Standard No. 82-16APage 32 Device standard (contd)up to VDDthrough a pullup resistor
31、.Package options include 96-ball LFBGA (MO-205CC).2.2 96-ball LFBGA (MO-205CC)Figure 1 Pinout configuration(TOP VIEW)JHGFEDCBA213465PNMLKTRJEDEC Standard No. 82-16APage 42 Device standard (contd)2.3 Pinout top view for 96-ball LFBGAFigure 2 1:1 Register (C0=0, C1=0)Figure 3 1:2 Register A (C0=0, C1=
32、1)ADCKE PPO VREFVDDQCKE DNUBD2 D15 GND GND Q2 Q15CD3 D16 VDDVDDQ3 Q16DDODT QERR GND GND QODT DNUED5 D17 VDDVDDQ5 Q17FD6 D18 GND GND Q6 Q18GPAR_IN RESET VDDVDDC1 C0HCK DCS GND GND QCS DNUJCK CSR VDDVDDNC NCKD8 D19 GND GND Q8 Q19LD9 D20 VDDVDDQ9 Q20MD10 D21 GND GND Q10 Q21ND11 D22 VDDVDDQ11 Q22PD12 D2
33、3 GND GND Q12 Q23RD13 D24 VDDVDDQ13 Q24TD14 D25 VREFVDDQ14 Q25123456ADCKE PPO VREFVDDQCKEA QCKEBBD2 DNU GND GND Q2A Q2BCD3 DNU VDDVDDQ3A Q3BDDODT QERR GND GND QODTA QODTBED5 NC VDDVDDQ5A Q5BFD6 NC GND GND Q6A Q6BGPAR_IN RESET VDDVDDC1 C0HCK DCS GND GND QCSA QCSBJCK CSR VDDVDDNC NCKD8 DNU GND GND Q8A
34、 Q8BLD9 DNU VDDVDDQ9A Q9BMD10 DNU GND GND Q10A Q10BND11 DNU VDDVDDQ11A Q11BPD12 DNU GND GND Q12A Q12BRD13 DNU VDDVDDQ13A Q13BTD14 DNU VREFVDDQ14A Q14B123456JEDEC Standard No. 82-16APage 52 Device standard (contd)2.3 Pinout top view for 96-ball LFBGA (contd)Figure 4 1:2 Register B (C0=1, C1=1)DNU den
35、otes do not use. NC denotes no internal connection.AD1 PPO VREFVDDQ1A Q1BBD2 DNU GND GND Q2A Q2BCD3 DNU VDDVDDQ3A Q3BDD4 QERR GND GND Q4A Q4BED5 DNU VDDVDDQ5A Q5BFD6 DNU GND GND Q6A Q6BGPAR_IN RESET VDDVDDC1 C0HCK DCS GND GND QCSA QCSBJCK CSR VDDVDDNC NCKD8 DNU GND GND Q8A Q8BLD9 DNU VDDVDDQ9A Q9BMD
36、10 DNU GND GND Q10A Q10BNDODT DNU VDDVDDQODTA QODTBPD12 DNU GND GND Q12A Q12BRD13 DNU VDDVDDQ13A Q13BTDCKE DNU VREFVDDQCKEA QCKEB123456JEDEC Standard No. 82-16APage 62 Device standard (contd)2.4 Terminal functions Data inputs = D2, D3, D5, D6, D8-D25 when C0=0 and C1=0Data inputs = D2, D3, D5, D6, D
37、8-D14 when C0=0 and C1=1Data inputs = D1-D6, D8-D10, D12, D13 when C0=1 and C1=1* Data outputs = Q2, Q3, Q5, Q6, Q8-Q25 when C0=0 and C1=0Data outputs = Q2, Q3, Q5, Q6, Q8-Q14 when C0=0 and C1=1Data outputs = Q1-Q6, Q8-Q10, Q12, Q13 when C0=1 and C1=1Table 1 Terminal functionsTerminalnameDescription
38、ElectricalcharacteristicsGND Ground Ground inputVDDPower supply voltage 1.8-V nominalVREFInput reference voltage 0.9-V nominalCK Positive master clock input Differential inputCK Negative master clock input Differential inputC0, C1Configuration control inputs - Register A or Register B and 1:1 mode o
39、r 1:2 mode selectLVCMOS inputsRESETAsynchronous reset input resets registers and disables VREFdata and clock differential-input receivers. When RESET is low all Q outputs are forced low and QERR output is forced high.LVCMOS inputCSR, DCS Chip select inputs disables D1-D24 outputs switching when both
40、 inputs are high SSTL_18 inputD1D25Data input clocked in on the crossing of the rising edge of CK and the falling edge of CKSSTL_18 inputDODT The outputs of this register bit will not be suspended by the DCS and CSR control. SSTL_18 inputDCKE The outputs of this register bit will not be suspended by
41、 the DCS and CSR control. SSTL_18 inputPAR_IN Parity input - arrives one clock cycle after the corresponding data input. SSTL_18 inputQ1Q25* Data outputs that are suspended by the DCS and CSR control. 1.8-V CMOS outputsPPO Partial parity out - indicates odd parity of inputs D1 - D25 1.8-V CMOS outpu
42、tQCS Data output that will not be suspended by the DCS and CSR control. 1.8-V CMOS outputQODT Data output that will not be suspended by the DCS and CSR control. 1.8-V CMOS outputQCKE Data output that will not be suspended by the DCS and CSR control. 1.8-V CMOS outputQERR Output error bit - Timing is
43、 determined by the device mode. Open-drain outputNC No internal connectionDNU Do not use - inputs are in standby-equivalent mode and outputs are driven low.JEDEC Standard No. 82-16APage 72 Device standard (contd)2.5 Function tableTable 2 Function table (each flip flop)Inputs OutputsRESET DCS CSR CK
44、CKDn, DODTn, DCKEnQn QCSQODT, QCKEHLLLLLLHLLHHLHH L L L or H L or H XQ0Q0Q0HLHLLLLHLHHHLHH L H L or H L or H XQ0Q0Q0HHLLLHLHHLHHHHH H L L or H L or H XQ0Q0Q0HHHLQ0HLHHHHQ0HHH H H L or H L or H XQ0Q0Q0LX or floatingX or floatingX or floatingX or floatingX or floatingLLLJEDEC Standard No. 82-16APage 8
45、2 Device standard (contd)2.5 Function table (contd) Data inputs = D2, D3, D5, D6, D8-D25 when C0=0 and C1=0Data inputs = D2, D3, D5, D6, D8-D14 when C0=0 and C1=1Data inputs = D1-D6, D8-D10, D12, D13 when C0=1 and C1=1* PAR_IN arrives one clock cycle (C0=0), or two clock cycles (C0=1), after the dat
46、a to which it applies* This transition assumes QERR is high at the crossing of CK going high and CK going low. If QERR is low, it stays latched low for a miminum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR out-put is driven low and latch
47、ed low for a clock duration equal to the parity duration or until RESET is driven low.Table 4 Parity Error Detect in Low-Power Mode If a parity error occurs before the device enters the low-power mode (LPM), the behavior of PPO and QERR is dependent on the mode of the device and the position of the
48、parity error occurrence. This table illustrates the low-power-mode effect on parity detect. The low-power mode is activated on the n clock cycle when DCS and CSR go high. The clock-edge position of a one-cycle data-input error relative to the clock-edge (n) which initiates LPM at the DCS and CSR inp
49、uts. If an error occurs, the PPO output may be driven high and the QERR output driven low. These columns show the clock duration for which the PPO signal will be held high or the QERR signal will be held low. Not used.Table 3 Parity and standby function tableInputs OutputsRESET DCS CSR CK CK of inputs = H(D1-D25)PAR_IN* PPO QERR*HLXEven L L HHLXOdd L H LHLX Even H H LHLXOdd H L HHHLEven L L HHHL Odd L H LHHLEven H H LHHLOdd H L HHHHXXPPO0QERR0H X X L or H L or H X XPPO0QERR0LX or floatingX or floating
