1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-19AMAY 2007JEDECSTANDARDDefinition of the SSTUA32S865DDR2 RDIMM Applications Registered Buffer with Parity forand SSTUA32D865 28-bit 1:2 (Revision of JESD82-19, May 2006)NOTICE JEDEC standards and publications contain material that has been prepared, re
2、viewed, and approvedthrough the JEDEC Council level and subsequently reviewed and approved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability
3、 andimprovement of products, and assisting the purchaser in selecting and obtaining with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted without regard to
4、 whether or not their adoption mayinvolve patents or articles, materials, or processes. By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information included in JEDEC standard
5、s and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and sugge
6、stions relative to the content of this JEDEC standard or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arling
7、ton, VA 22201-3834 This document may be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Pu
8、blications online at http:/www.jedec.org/Catalog/catalog.cfm. Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to repr
9、oduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-19APage 1DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-B
10、IT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS(From JEDEC Board Ballot JCB-05-127 and JCB-07-07, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, switching parameters, and test
11、loading for definition of the SSTUA32S865 and SSTUA32D865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications.The SSTUA32S865 and SSTUA32D865 are identical in functionality to the SSTU32865 but specify tighter timing characteristics and a higher application
12、frequency of up to 410MHz.SSTU32S865 denotes a single-die implementation, SSTU32D865 denotes a dual-die implementation.The purpose is to provide a standard for the SSTUA32S865 and SSTUA32D865 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device s
13、pecification, and ease of use.NOTE The designation SSTUA32S865 and SSTUA32D865 refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.2 Device
14、 standard2.1 DescriptionThis 28-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDDoperation.All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2
15、 DIMM load.The SSTUA32S865 and SSTUA32D865 operate from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and un
16、driven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level.To ensure defined outputs from the regist
17、er before a stable clock has been supplied, RESET must be held in the low state during power up.JEDEC Standard No. 82-19APage 22 Device standard (contd)2.1 Description (contd)In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timi
18、ng relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative
19、 to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SSTUA32S865 and SSTUA32D865 must ensure that the outputs will r
20、emain low, thus ensuring no glitches on the output. If the data inputs are not held low, then DCS0 and DCS1 must be held high, DODT0 and DODT1, DCKE0, and DCKE1 must be held low, and all other inputs must remain stable (either low or high) for a minimum of tACT(max) after the rising edge of RESET.Th
21、e device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 or DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low an
22、d the PTYERR output high. If the DCS-control functionality is not desired, then the CSGateEnable input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs.The SSTUA32S865 and SSTUA32D865 include a parity checking function. Th
23、e SSTUA32S865 and SSTUA32D865 accept a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs (with either DCS0 or DCS1 active) and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).The parity error outpu
24、t PTYERR will be reset to high by RESET transitioning low and will not be decoded until after RESET goes high and DCS0 and/or DCS1 are asserted low. CSGateEN does not affect PTYERR operation.Package options include 160-ball Thin Profile Fine Pitch BGA (TFBGA) (12 18 array, 9.0 13.0 mm body size, 0.6
25、5 mm pitch, MO-246, Issue A).JEDEC Standard No. 82-19APage 32.2 160-ball TFBGA (MO-246A)Figure 1 Pinout configurationJEDEC Standard No. 82-19APage 42.3 Pinout top view for 160-ball TFBGAAn empty cell indicates no ball is populated at that gridpoint. NC denotes a no-connect (ball present but not conn
26、ected to the die). MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH.Figure 2 Pinout top view for 160-ball TFBGA (12 18 grid)12345678910112A VREF NC PARIN NC NC QCKE1A QCKE0A Q21A Q19A Q18A Q17B Q17AB D1 D2 NC NC NC QCKE1B QCKE0B Q21B Q19B Q18B QODT0B QODT0A
27、C D3 D4 QODT1B QODT1AD D6 D5 VDDL GND NC NC GND GND Q20B Q20AE D7 D8 VDDL GND VDDL VDDR GND GND Q16B Q16AF D11 D9 VDDL GND VDDR VDDR Q1B Q1AG D18 D12 VDDL GND VDDR VDDR Q2B Q2AHCSGate END15 VDDL GND GND GND Q5B Q5AJ CK DCS0 GND GND VDDR VDDR QCS0B QCS0AK CK DCS1 VDDL VDDL GND GND QCS1B QCS1AL RESET
28、D14 GND GND VDDR VDDR Q6B Q6AM D0 D10 GND GND GND GND Q10B Q10AN D17 D16 VDDL VDDL VDDR VDDR Q9B Q9AP D19 D21 GND VDDL VDDL VDDR VDDR GND Q11B Q11AR D13 D20 GND VDDL VDDL GND GND GND Q15B Q15AT DODT1 DODT0 Q14B Q14AU DCKE0 DCKE1 MCL PTYERR MCH Q3B Q12B Q7B Q4B Q13B Q0B Q8BV VREF MCL MCL NC MCH Q3A Q
29、12A Q7A Q4A Q13A Q0A Q8AJEDEC Standard No. 82-19APage 52.4 Terminal functionsTable 1 Terminal functionsSignal Group Signal Name Type DescriptionUngated inputs DCKE0, DCKE1, DODT0, DODT1SSTL_18 DRAM function pins not associated with Chip Select.Chip Select gated inputsD0 . D21 SSTL_18 DRAM inputs, re
30、-driven only when Chip Select is LOW.Chip Select inputsDCS0, DCS1 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command decodes and parity checking, and as such at least one will be low when a valid address/command is present. The register can be programmed to re-drive all D-inp
31、uts only (CSGateEN high) when at least one Chip Select input is LOW. Re-driven outputsQ0A.Q21A, Q0B . Q21B, QCS0-1A,B, QCKE0-1A,B, QODT0-1A,BSSTL_18 Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock.Parity input PARIN SSTL_18 Parity i
32、nput for the D0 . D21 inputs; arrives one clock cycle after the corresponding data input.Parity error outputPTYERR Open drain When LOW, this output indicates that a parity error was identified associated with a valid address and/or command input. PTYERR will be active for two clock cycles, and delay
33、ed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition).Program inputs CSGateEN 1.8 V LVCMOSChip Select Gate Enable. When HIGH, the D0D21 inputs will be latched only when at least one Chip Select input
34、is LOW during the rising edge of the clock. When LOW, the D0.D21 inputs will be latched and redriven on every rising edge of the clock.Clock inputs CK, CK SSTL_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (C
35、K).Miscellaneous inputsMCL, MCH Must be connected to a logic LOW or HIGH.RESET 1.8 V LVCMOSAsynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal.VREF 0.9 V nominal Input reference voltage for the SSTL_18 in
36、puts. Two pins (internally tied together) are used for increased reliability.JEDEC Standard No. 82-19APage 62 Device standard (contd)2.5 Function tableTable 2 Function table (each flip flop)Inputs OutputsRESET DCS0 DCS1CSGate EnableCK CKDn, DODTn, DCKEnQn QCS0QCS1QODT, QCKEHLL X LLLLLHLL X HHLLHH L
37、L X L or H L or H XQ0Q0Q0Q0HLH X LLLHLHLH X HHLHHH L H X L or H L or H XQ0Q0Q0Q0HHL X LLHLLHHL X HHHLHH H L X L or H L or H XQ0Q0Q0Q0HHH L LLHH LHHH L HHHH HH H H L L or H L or H XQ0Q0Q0Q0HHHHLQ0HH LHHHHHQ0HH HH H H H L or H L or H XQ0Q0Q0Q0LX or floatingX or floatingX or floatingX or floatingX or f
38、loatingX or floatingLL L LJEDEC Standard No. 82-19APage 72 Device standard (contd)2.5 Function table (contd)Table 3 Parity and standby function tableInputs OutputRESET DCS0 DCS1 CK CK of inputs = H(D0-D21)PARIN* PTYERR*HLHEven L HHLHOdd L LHLH Even H LHLHOdd H HHHLEven L HHHL Odd L LHHLEven H LHHLOd
39、d H HHHHXXPTYERR0H X X L or H L or H X XPTYERR0LX or floatingX or floatingX or floatingX or floatingX or floatingX or floatingH* PARIN arrives one clock cycle after the data to which it applies. All D inputs must be driven to a known state for parity to be calculated correctly.* This transition assu
40、mes PTYERR is high at the crossing of CK going high and CK going low. If PTYERR is low, it stays latched low for two clock cycles or until RESET is driven low. CSGateEN is “dont care” for PTYERR. If DCS0, DCS1, and CSGEN are driven high, the device is placed in low-power mode (LPM). If a parity erro
41、r occurs on the clock cycle before the device enters the LPM and the PTYERR output is driven low, it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low.JEDEC Standard No. 82-19APage 82 Device standard (contd)2.6 Logic diagramFigure 3 Logic diagram (positive log
42、ic)DQRDQRDQRDQRDQRDQRDQRPARIND0D21VREF(CS ACTIVE) DCS0DCS1DCKE0,DCKE1DODT0,DODT1CSGateENRESETCKCK22PARITYGENERATORANDCHECKERQ0AQ0BQ21AQ21BQCS0AQCS0BQCS1AQCS1BQCKE0A,QCKE1AQCKE0B,QCKE1BQODT0A,QODT1AQODT0B,QODT1BPTYERR2222002aaa386JEDEC Standard No. 82-19APage 92 Device standard (contd)2.7 Register ti
43、mingFigure 4 RESET switches from L to H(1) After RESET is switched from LOW to HIGH, if DCS0 or DCS1 are held Low than all data and PAR_IN input signals must be held Low for a minimum time of tACT(max.) to avoid false error. If DCS0 or DCS1 are held high than all data and PAR_IN input signals must b
44、e held at valid logic levels for a minimum time of tACT(max.) to avoid false error.CKDn(1)Qntsu002aaa983CKn n + 1 n + 2 n + 3 n + 4DCSnRESETtACT thtPDM, tPDMSSCK to QPARINtsuthtPHL, tPLHCK to PTYERRtPHLCK to PTYERRPTYERRH, L, or X H or LJEDEC Standard No. 82-19APage 102 Device standard (contd)2.7 Re
45、gister timing (contd)Figure 5 RESET being held HIGHCKDn(1)Qntsu002aaa984CKn n + 1 n + 2 n + 3 n + 4DCSnRESETthtPDM, tPDMSSCK to QPARINthtPHL, tPLHCK to PTYERRPTYERROutput signal is dependent on the prior unknown eventH or LUnknown input eventtsuJEDEC Standard No. 82-19APage 112 Device standard (cont
46、d)2.7 Register timing (contd)Figure 6 RESET switches from H to L(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not floating) for a minimum time of tINACT(max.).CK(1)DCSnRESETtINACTtRPHLRESET to QPARIN(1)tRPLHRESET to PTYERRP
47、TYERRH, L, or X H or LCK(1)Dn(1)Qn002aaa985JEDEC Standard No. 82-19APage 122 Device standard (contd)2.7 Register timing (contd)Figure 7 Timing diagram during start-up when data inputs are Low or High (RESET switches from L to H)After REST is switched from low to high, DCS0 and DSC1 must be held HIGH
48、, DODT0, DODT1, DCKE0 and DCKE1 must be held LOW, and all other inputs must remain stable either LOW or HIGH (not floating) for a minimum time of tACTmax. nCKCKRESET3 nstACTn+1 n+2 n+3 n+4PTYERRDCS0DODTn,DCKEnDnPAR_INQCSnQODTn,QCKEnQnDCS1H or LH, L or XJEDEC Standard No. 82-19APage 132 Device standa
49、rd (contd)2.7 Register timing (contd)Figure 8 Data error occurs at (n-1), LPM occurs at (n)2.8 Parity logic diagramFigure 9 Parity logic diagramn-1 n n+1 n+2 m m+1 m+2()()()()()()()()()()()()Low Power Mode (LPM)CKData ErrorPARINDCSnPTYERR()()CSGateEND22DD LATCHING AND RESET FUNCTIONsee Note (1)PTYERRDQnAQnBDnPARINCLOCKQ002aaa41722(1) This function holds the error for two cycles. See functional description and timing diagram.JEDEC Standard No. 82-19APage 142 Device standard (contd)2.9 Absolute ma
