1、JEDEC STANDARD FBDIMM Advanced Memory Buffer (AMB) JESD82-20A (Revision of JESD82-20, March 2007) MARCH 2009 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION SPECIAL DISCLAIMER: JEDEC has received information that certain patents or patent applications may be relevant to this standard, and, as of the public
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12、andard, and, as of the publication date of this standard, no statements regarding an assurance or refusal to license such patents or patent applications have been provided. http:/www.jedec.org/download/search/FBDIMM/Patents.xls JEDEC does not make any determination as to the validity or relevancy of
13、 such patents or patent applications. Prospective users of the standard should act accordingly. JEDEC Standard No. 82-20AiFBDIMM: Advanced Memory Buffer (AMB)ContentsContents . iList of Tables . vList of Figures . vi1 Introduction.11.1 Advanced Memory Buffer Overview .11.2 Advanced Memory Buffer Fun
14、ctionality11.2.1 Advanced Memory Buffer .11.2.2 Transparent Mode for DRAM Test Support21.2.3 Debug and Logic Analyzer Interface 21.2.4 DDR SDRAM21.3 Advanced Memory Buffer Block Diagram.31.4 Interfaces41.4.1 FBD High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces .41.4.2 DDR2 Channel .
15、41.4.3 SMBus Slave Interface .51.5 References .51.6 Glossary .52 FBD Channel Interface .82.1 Advanced Memory Buffer Support for FBD Operating Modes .82.2 Channel Initialization 82.3 Channel Protocol 82.3.1 General.82.3.2 Timeouts during TS0 82.3.3 Recalibrate state considerations 92.3.4 Address Mapp
16、ing of DDR Commands to DRAMs 102.3.5 FBD L0s State 102.4 Reliability, Availability, and Serviceability .112.4.1 General.112.4.2 Channel Error Detection and Logging 112.5 Channel Configuration112.5.1 Re-sync and Resample Modes 112.5.2 Other Channel Configuration Modes 122.5.3 Lane to Lane Skew on a C
17、hannel 122.6 Repeater Mode.132.7 Performance .132.7.1 Idle Memory Read Latency.132.8 AMB Components of Channel Latency 142.8.1 Command to Data Delay Calculation .152.8.2 Channel Throughput.173 DDR Interface183.1 Advanced Memory Buffer DDR Interface Overview .183.2 Data Mapping .183.2.1 Data Mask 183
18、.3 Command / Address Outputs .193.3.1 CKE Output Control20JEDEC Standard No. 82-20AiiFBDIMM: Advanced Memory Buffer (AMB)Contents (contd)3.3.2 Memory Controller / BIOS requirements 203.4 DQS I/O and DM Outputs.213.5 Refresh .223.5.1 Self-Refresh During Channel Reset .223.5.2 Automatic Refresh 223.6
19、Back to Back Turnaround Time 233.7 DDR Calibration233.7.1 DRAM Initialization and (E)MRS 243.7.2 Automatic DDR Bus Calibration .243.7.3 S3 Recovery Configuration Registers 253.7.4 Receive Enable Calibration 253.7.5 DQS Delay Calibration .253.8 DDR MEMBIST 253.8.1 MEMBIST Features 263.9 DIMM Organiza
20、tion.284 Electrical, Power, and Thermal .294.1 Electrical DC Parameters .294.1.1 Absolute maximum ratings .294.1.2 Normal Mode 304.1.3 S3 current Specification374.2 FBD Channel Interface .374.2.1 FBD Electrical Timing Specifications374.2.2 AMB Latency Parameters.384.3 DDR2 DRAM Interface Electrical
21、Specifications 424.4 DDR2 Electrical Output Timing Specifications .434.4.1 Description of DQ/DQS Alignment .434.4.2 Description of ADD/CMD/CNTL Outputs434.4.3 Test Load Specification 434.4.4 tDVA and tDVB Parameter Description 434.4.5 tjit and tjitHP Parameter Description.444.4.6 tCVA, tCVB, tECVA a
22、nd tECVB Parameter Description 444.4.7 tDQSCK Timing Parameter Description .454.4.8 DQ and CB (ECC) Setup/Hold Relationships to/from DQS (Read Operation) .454.4.9 Write Preamble Duration 464.4.10 Write Postamble Duration.464.4.11 Advance Memory Buffer Component Electrical Timing Summary474.4.12 Refe
23、rence DDR2 Interface Package Trace Lengths 484.5 SMBUS Interface.494.6 Misc I/O (1.5 CMOS Driver)494.7 Thermal Diode and Analog to Digital Converter (ADC) 504.7.1 Thermal Sensor Effects on the Advanced Memory Buffers Functional Behavior 505 Error Handling 515.1 Types of Errors and Responses .515.1.1
24、 FBD Link Errors 515.1.2 DDR Errors .525.1.3 Host Protocol Errors .535.1.4 Other Errors53JEDEC Standard No. 82-20AiiiFBDIMM: Advanced Memory Buffer (AMB)Contents (contd)5.2 Error Logging545.2.1 Error Logging Procedure 545.3 Fail Over Mode Support .545.4 Failback to Pass-Thru.546 Transparent Mode 556
25、.1 Transparent Mode 556.1.1 Block Diagram 556.1.2 Transparent Mode Signal Definitions .566.1.3 Transparent Mode to FBD Pin Mapping .576.1.4 Clock Frequency and Core Timing .576.1.5 Transparent mode timing586.1.6 Error reporting 626.1.7 Transparent mode I/O specifications646.1.8 I/O implementation gu
26、idelines 656.2 Transparent Mode Control and Status Registers .667 SMBus Interface .677.1 System Management Access .677.1.1 SMBus 2.0 Specification Compatibility .677.1.2 Supported SMBus Commands .677.1.3 FBD AMB Register Access Protocols.687.1.4 SMBus Error Handling717.1.5 SMBus Resets728 Clocking 7
27、38.1 Advanced Memory Buffer Clock Domains738.2 PLL Clocks .738.3 Reference Clock .738.4 FBD Lane Frame Clocks 738.5 Clock Ratios .748.6 DDR DRAM Clock Support.748.7 Clock Pins.748.8 PLL Requirements758.8.1 Jitter758.8.2 PLL Bandwidth Requirements 758.8.3 External Reference.758.8.4 Spread Spectrum Su
28、pport 758.9 Analog Power Supply Pins .759 Pin Descriptions .769.1 Pin Description .7610 Reset7910.1 Introduction.7910.2 Platform Reset Functionality.7910.2.1 Platform RESET# Requirements7910.2.2 Advanced Memory Buffer RESET# Requirements.7910.2.3 Power-Up and Suspend-to-RAM Considerations .8010.3 Re
29、set Types .80JEDEC Standard No. 82-20AivFBDIMM: Advanced Memory Buffer (AMB)Contents (contd)10.4 Pads Controlling Reset.8010.4.1 RESET# Pad 8010.4.2 Primary FBD Link .8010.5 Details.8110.5.1 Cold Power-Up Reset Sequence8110.6 Timing Diagrams 8210.7 I/O Initialization .8210.7.1 FBD Channel Initializa
30、tion 8211 Registers 8311.1 Access Mechanisms.8311.1.1 Conflict Resolution and Usage Model Limitations 8311.1.2 FBD Data on Configuration Read Returns .8311.1.3 Non-Existent Register Bits8311.1.4 Register Attribute Definition8411.1.5 Binary Number Notation .8411.1.6 Function Mapping .8411.2 PCI Stand
31、ard Header Identification Registers (Function 0)9411.2.1 VID: Vendor Identification Register 9411.2.2 DID: Device Identification Register.9411.2.3 RID: Revision Identification Register 9411.2.4 CCR: Class Code Register.9511.2.5 HDR: Header Type Register.9511.3 FBD Link Registers (Function 1) 9611.3.
32、1 FBD Link Control and Status 9611.3.2 Error Registers .10911.3.3 PERSONALITY BYTES loaded from the SPD .11111.3.4 Advanced Memory Buffer Hardware Configuration Registers11211.4 Implementation Specific FBD Registers (Function 2).11411.5 DDR and Miscellaneous Registers (Function 3).11511.5.1 Memory B
33、IST Registers .11511.5.2 Memory Registers 12311.5.3 Thermal Sensor Registers12811.6 Implementation Specific DDR Initialization and Calibration Registers (Function 4) .13111.6.1 DDR Calibration13111.7 DFX Registers (Function 5) 13411.7.1 Transparent Mode Registers 13411.7.2 Logic Analyzer Interface (
34、LAI) Registers 13611.7.3 Error Injection Registers .15611.8 Bring-up and Debug Registers (Function 6) .14711.8.1 Southbound FBD IBIST registers .14711.8.2 Northbound FBD IBIST registers15312 Ballout and Package Information15912.1 655-ball FBGA, Pin configuration 15912.2 Pin Assignments for the Advan
35、ced Memory Buffer (AMB).16012.3 Package Information.168JEDEC Standard No. 82-20AvFBDIMM: Advanced Memory Buffer (AMB)Contents (contd)13 AMB Quad Rank Support.16913.1 Background 16913.2 AMB signal changes and DRAM connections 16913.2.1 Quad Rank Signal Requirements .16913.2.2 Address and Control sign
36、al reuse 17013.2.3 Quad Rank Signal Mapping17113.2.4 Mapping to AMB balls.17213.2.5 Signal state at reset17213.3 Rank Decode17213.3.1 Quad Rank Mode C17313.3.2 FBD2 Mode A Rank Decode 17613.4 ODT timing on reads 17813.4.1 AMB data bus termination 17813.5 Registers 17913.6 Fast Reset 182Tables1 Examp
37、le FBD-667 Channel Idle Memory Read Latencies. 142 DQS association with DQ/CB pins in x8 and x4 mode. 213 MEMBIST Feature Summary . 274 Absolute maximum ratings over operating free-air temperature range (see Note 1) . 295 Advanced Memory Buffer Normal Mode DC Electrical Parameters. 305A Advanced Mem
38、ory Buffer Normal Mode DC+AC Electrical Parameters 306 AMB Power Specification Parameters and Test Conditions 306A Table 6 values for x8 DIMMs . 326B Table 6 values for x4 DIMMs . 327 Advanced Memory Buffer FBD Timing/Electrical . 378 Recommended operating conditions for DRAM Interface 429 Advance M
39、emory Buffer Component DDR2 Electrical Timing Specifications 4710 Advance Memory Buffer DDR2 Package Lengths . 4811 Recommended operating conditions for SMBUS Interface 4912 Recommended operating conditions for RESET and BFUNC pins 4913 Link Errors in Initialization 5114 Link Errors in Normal Operat
40、ion. 5115 DDR Errors. 5216 Host Protocol Errors. 5317 Other Errors . 5318 Additional Signals in Transparent Mode 5619 Mapping of FBD Pins in Transparent Mode . 5720 Mapping of burst position bits to error capture. 6321 Selection of 8 bit data paths when ENDOUT is set 6422 Transparent mode FB-DIMM in
41、terface signaling specifications. 6423 SMBus command Encoding. 6824 SMBus Protocol Addressing fields . 6825 Status Field Encoding for SMBus Reads .6926 Advanced Memory Buffer Clock Ratios 7427 Clock Pins 7428 Buffer Signal Types 7629 Pin Descriptions . 76JEDEC Standard No. 82-20AviFBDIMM: Advanced M
42、emory Buffer (AMB)Contents (contd)30 Access to “Non-existent” Register Bits. 8331 Register Attributes Definitions 8432 Function Mapping Legend 8533 Function 0: PCI Standard Header Identification Registers. 8634 Function 1: FBD Link Registers . 8735 Function 2: Implementation Specific FBD Registers 8
43、836 Function 3: DDR and Miscellaneous Registers 8937 Function 4: Implementation Specific DDR Initialization and Calibration Registers 9038 Function 5: DFX Registers . 9139 Function 6: IBIST, Bring-up and Debug Registers . 9240 Functions 7: FBD DFX/Defeature Registers 9341 Functional mapping of MemBI
44、ST data fields by test mode 11942 MBDATA Failure Address register correspondence to DRAM address. 12043 BL4 Column and Chunk correspondence to DRAM address. 12044 BL8 Column and Chunk correspondence to DRAM address. 12045 Functional Characteristics of DCALADDR . 13246 Bit Locations for SB Match and
45、Mask 13747 Local Mask and Match Events selected by MMEVENTnSEL fields. 14048 655-Ball FBGA - Left Side 16049 655-Ball FBGA - Right Side . 16150 Advanced Memory Buffer Signals by Ball Number 16251 Function Mapping Lege72 16952 Quad Rank Signal mapping per rank, ODT Option 1. 17153 Quad Rank Signal ma
46、pping per rank, ODT Option 2. 17154 AMB Pin usage for each DIMM type 17255 RS1:0 to rank decode 17356 dBA0 (DRAM BA0) Selection by DRAM density 17357 DIMM addressing . 17358 Activate Command mapping 17459 Read, Write & Precharge Single Command mapping 17560 Rank Selection and dBA0 generation for eac
47、h command type 17561 Quad Rank Mode A DS2:0 and RS mapping. 17662 AMB response to commands . 177Figures1 Advanced Memory Buffer Block Diagram 32 Advanced Memory Buffer Interfaces 43 Delays Through an AMB 154 Command to Data Delay timing . 165 Nominal Turnaround Time Timing Diagram . 236 tDVA and tDV
48、B Timing Diagram 447 tjit and tjitHP Timing Diagram. 448 tCVA and tCVB Timing Diagram 449 tECVA and tECVB Timing Diagram .4510 TDQSCK Timing Diagram 4511 DQ and CB (ECC) Setup/Hold Relationship to/from DQS Timing Diagram. 4612 Write Preamble Duration Timing Diagram4613 Write Postamble Duration Timin
49、g Diagram 4614 Transparent Mode Simplified Block Diagram. 5515 Transparent Mode Timing 5916 Transparent mode write timing. 6017 Transparent mode read timing . 61JEDEC Standard No. 82-20AviiFBDIMM: Advanced Memory Buffer (AMB)Contents (contd)18 BL=8 Read timing. 6219 SMBus Configuration Read (Block Write / Block Read, PEC enabled) 6920 SMBus Configuration Read (Write Bytes / Read Bytes, PEC enabled) . 7021 SMBus Configuration Double Word Write (Block Write, PEC enabled) . 7022 SMBus Configuration Double Word Write (Write Bytes, PEC enabled). 7123 SMBus Configuration Word Write (Bl
