1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-21JANUARY 2007JEDECSTANDARDStandard for Definition of CUA845PLL Clock Driver for Registered DDR2 DIMM ApplicationsNOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Director
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6、is JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains
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8、onal (303) 397-7956 Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the Electronic Industries Alliance and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering in
9、to a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-21Page 1STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVERFOR REGISTERED DDR2 DIMM APPLICATIONS(From JEDEC Boar
10、d Ballot JCB-06-67, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The p
11、urpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. 2 Definitions for the purpose of this documentCI() Delta input capacitance.t(su) Sum of the Setup-time skew parameters.t(h)
12、 Sum of the Hold-time skew parameters.3 Device standard3.1 DescriptionThis PLL Clock Buffer is designed for a VDDQ of 1.8 V, an AVDDof 1.8 V and differential data input and output levels. Package option includes a plastic 28-ball BGA.The device is a zero delay buffer that distributes a differential
13、clock input pair (CK, CK) to five differential pair of clock outputs (Y0:4, Y0:4) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS (OE, OS) and the Analog Power input (AVDD). W
14、hen OE is low, the outputs (except FBOUT/FBOUT) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on Y3/Y3 (th
15、ey are free running in addition to FBOUT/FBOUT). When AVDDis grounded, the PLL is turned off and bypassed for test purposes.When both clock signals (CK, CK) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input
16、buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obta
17、in phase lock between the feedback clock pair (FBIN, FBIN) and the input clock pair (CK, CK) within the specified stabilization time tL.The PLL in the CUA845 clock driver uses the input clocks (CK, CK) and the feedback clocks (FBIN, FBIN) to provide high-performance, low-skew, low-jitter output diff
18、erential clocks (Y0:4, Y0:4). The CUA845 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.The CUA845 is characterized for operation from 0oC to 70 oC.JEDEC Standard No. 82-21Page 23.1 Description (contd)TopviewFigure 1 28-Ball BGA (5x6 Array, 4.0x4.5 mm Body Size, 0.65 mm Pitch,
19、MO-TBD) package pinoutY0 Y0# Y1# Y1 FBINCK VDDQ NB VDDQ FBIN#CK# OE VDDQ OS FBOUT#AGND GND VDDQ GND FBOUTAVDD GND NB GND Y2Y4 Y3# Y3 Y2#Y4#EABCDF12 453JEDEC Standard No. 82-21Page 33.2 Terminal functions3.3 Function table* L(Z)means the outputs are disabled to a low state meeting the IODLlimit in Ta
20、ble 5.Table 1 Terminal FunctionsTerminalNameDescriptionElectricalCharacteristicsAGND Analog Ground GroundAVDDAnalog power 1.8 V nominalCK Clock input with a (10K-100K Ohm) pulldown resistor Differential inputCK Complementary clock input with a (10K-100K Ohm) pulldown resistor Differential inputFBIN
21、Feedback clock input Differential inputFBIN Complementary feedback clock input Differential inputFBOUT Feedback clock output Differential outputFBOUT Complementary feedback clock output Differential outputOE Output Enable (Asynch) LVCMOS inputOSOutput Select (tied to GND or VDDQ)LVCMOS inputGND Grou
22、nd GroundVDDQLogic and output power 1.8 V nominalY0:4 Clock outputs Differential outputsY0:4 Complementary clock outputs Differential outputsNB No ballTable 2 Function tableInputs OutputsPLLAVDDOE OS CK CK YYFBOUT FBOUTGND H X L H L LHBypassed/OffGND H X H L HL LBypassed/OffGND L H L H*L(Z)*L(Z) LHB
23、ypassed/OffGND L L H L*L(Z),Y3 active*L(Z),Y3 activeHLBypassed/Off1.8V(nom) LHLH*L(Z)*L(Z) LHOn1.8V(nom) LLHL*L(Z),Y3 active*L(Z),Y3 activeHL On1.8V(nom) HXLHLHLHOn1.8V(nom) H X H L HLHL On1.8V(nom) XXLL*L(Z)*L(Z)*L(Z)*L(Z)Off1.8V(nom) HH ResrvedJEDEC Standard No. 82-21Page 43.4 Logic diagramFigure
24、2 Logic diagram (positive logic)JEDEC Standard No. 82-21Page 53.5 Absolute maximum ratingsTable 3 Absolute maximum ratings over operating free-air temperature range (see Note 1)Supply voltage range, VDDQor AVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5
25、V to 2.5 VInput voltage range, VI(see Notes 2 and 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDQ+ 0.5 VOutput voltage range, VO(see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDQ+ 0.5 VInput clamp current, IIK(VIVDDQ). . .
26、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAOutput clamp current, IOK(VOVDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous output current, IO(VO= 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27、. . . . . . . . . . . . . 50 mAContinuous current through each VDDQor GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mAStorage temperature range, TSTG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C to
28、 150 CNOTE 1 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
29、Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2 The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.NOTE 3 This value is limited to 2.5 V maximum.3.6 Recommended operating conditionsN
30、OTE 1 The PLL is turned off and bypassed for test purposes when AVDDis grounded. During this test mode, VDDQremains within the recommended operationing conditions and no timing parameters are guaranteed.NOTE 2 VIDis the magnitude of the difference between the input level on CK and the input level on
31、 CK, see Figure 12 for definition. For CK and CK the VIHand VILlimits are used to define the DC low and high levels for the logic detect state. Table 4 Recommended operating conditions (see Note 1)Min Nom Max UnitVDDQOutput supply voltage 1.7 1.8 1.9 VAVDDSupply voltage, see Note 1VDDQVILLow-level i
32、nput voltage, see Note 2OE, OS, CK, CK0.35 x VDDQVVIHHigh-level input voltage, see Note 2OE, OS, CK, CK0.65 x VDDQVIOHHigh-level output current, see Figure 5 9 mAIOLLow-level output current, see Figure 5 9 mAVIXInput differential-pair cross voltage(VDDQ/2)-0.15 (VDDQ/2)+0.15VVINInput voltage level 0
33、.3VDDQ+ 0.3VVIDInput differential voltage,see Note 2 and Figure 12DC 0.3VDDQ+ 0.4VAC 0.6VDDQ+ 0.4VTAOperating free-air temperature 0 70 CJEDEC Standard No. 82-21Page 63.7 DC specificationsNOTE 1 Total IDD= IDDQ+IADD= FCK* CPD* VDDQ, solving for CPD= (IDDQ+IADD)/(FCK*VDDQ) where FCKis the input Frequ
34、ency, VDDQis the power supply and CPDis the Power Dissipation Capacitance.Table 5 Electrical characteristics over recommended operating free-air temperature rangePARAMETER TEST CONDITIONSAVDD, VDDQMIN TYP MAX UNITVIKAll inputs II= 18 mA1.7 V 1.2 VVOHHigh output voltageIOH= 100 A1.7 to 1.9 VVDDQ-0.2V
35、IOH= 9 mA1.7 V 1.1VOLLow output voltageIOL= 100 A1.7 to 1.9 V 0.1VIOL= 9 mA1.7 V 0.6IODLOutput disabled low currentOE = L, VODL= 100mV1.7 V 100 AVODOutput differential voltage, the magnitude of the difference between the true and complimentary outputs, see Figure 12 for definition.1.7 V 0.6 VIICK, C
36、KVI= VDDQor GND1.9 V 250AOE, OS, FBIN, FBINVI= VDDQor GND1.9 V 10IDDLDStatic supply current, IDDQ+ IADDCK and CK = L 1.9 V 500 AIDDDynamic supply current,IDDQ+ IADD, see Note 1 for CPDcalculationCK and CK = 410 MHz,all outputs are open (not connected to a PCB)1.9 V 300 mACICK and CKVI= VDDQor GND1.8
37、 V23pFFBIN and FBIN VI= VDDQor GNDCI()CK and CK VI= VDDQor GND0.25FBIN and FBIN VI= VDDQor GND0.25JEDEC Standard No. 82-21Page 73.8 Timing requirementsNOTE 1 The PLL must be able to handle spread spectrum induced skew.NOTE 2 Operating clock frequency indicates a range over which the PLL must be able
38、 to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.)NOTE 3 Application clock frequency indicates a range over which the PLL must meet all timing parameters.NOTE 4 Stabilization time is the time required for the integrated PLL circuit to ob
39、tain phase lock of its feedback signal to its reference signal, within the value specificied by the Static Phase Offset (t(), after power-up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its re
40、ference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. Table 6 Timing requirements over recommended operating free-air temperature range.AVDD,
41、VDDQ= 1.8 V 0.1 VUNITMIN MAXfCKOperating clock frequency (see Notes 1 and 2) 125 410 MHzApplication clock frequency (see Notes 1 and 3) 160 410 MHztDCInput clock duty cycle 40 60 %tLStabilization time (see Notes 4) 6 sJEDEC Standard No. 82-21Page 83.9 AC specificationsTable 7 Switching characteristi
42、cs over recommended operating free-air temperature range(unless otherwise noted) (see Note 6)NOTE 1 Static Phase Offset does not include Jitter.NOTE 2 Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.DESCRIPTION DIAGRAMfCK(M
43、Hz)AVDD, VDDQ= 1.8 V 0.1 VUNITMIN Nom MAXtenOE to any Y/Y see Figure 14 160 to 410 8 nstdisOE to any Y/Y see Figure 14 160 to 410 8 nsslr(i)Output Enable (OE) see Figure 12 160 to 410 0.5 V/nsInput clock slew rate, measured single ended.see Figure 12 160 to 410 1 2.5 4 V/nsslr(o)Output clock slew ra
44、te, measured single ended. (see Notes 3, 5)see Figures 4 and 12160 to 410 1.5 2.5 3 V/nsVOXOutput differential-pair cross- voltage, (see Note 4)see Figure 5 160 to 410(VDDQ/2) - 0.1(VDDQ/2) + 0.1Vtjit(cc+)Cycle-to-cycle period jitter see Figure 7 160 to 410040pstjit(cc-) 0 40 pst()Static phase offse
45、t (see Note 1)see Figure 8 160 to 410 50 50 pst()dynDynamic phase offset(see Note 7)see Figure 13160 to 270 50 50 ps271 to 410t()dyn(min)t()dyn(max)pstsk(o)Output clock skew(see Note 7)see Figure 9160 to 270 40 ps271 to 410tsk(o)maxpstjit(per)Period jitter(see Notes 2, 7)see Figure 10160 to 270 40 4
46、0 ps271 to 410tjit(per)mintjit(per)maxpstjit(hper)Half-period jitter(see Note 2)see Figure 11160 to 270 75 75 ps271 to 410 50 50 pst(su)|tjit(per)| + |t()dyn| + tsk(o)(see Note 7)271 to 410 80 pst(h)|t()dyn| + tsk(o)(see Note 7)271 to 410 60 psThe PLL in the CUA845 must be capable of meeting all the
47、 above test parameters while supporting SSC synthesizers with the following parameters: SSC modulation frequency 30.00 33 kHzSSC clock input frequency deviation0.00 0.50 %CUA845 PLL designs should target the values below to minimize the SSC induced skew:PLL Loop bandwidth (-3 dB from unity gain)2.0
48、MHzJEDEC Standard No. 82-21Page 93.9 AC Specifications (cont.)NOTE 3 The Output Slew Rate is determined from the IBIS model into the load shown in Figure 4. It is measured single ended.NOTE 4 VOXspecified at the DRAM clock input or the test load.NOTE 5 To eliminate the impact of input slew rates on
49、static phase offset, the input slew rates of Reference Clock Input CK,CK and Feedback Clock Input FBIN, FBIN are recommended to be nearly equal. The 2.5 V/ns slew rates are shown as a recommended target. Compliance with these Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2 DIMM application. NOTE 6 There are two different terminations that are used with the above ac tests. The load/board in Figure 5 is used to
