1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-26JEDECSTANDARDDefinition of the SSTUB32868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM ApplicationsMAY 2007NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level an
2、d subsequently reviewed and approved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchas
3、er in selecting and obtaining with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents or a
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5、uct specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard
6、or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded fre
7、e of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications at www.jedec.org Printed in the U.S.A. All
8、rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For informat
9、ion, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-26Page 1DEFINITION OF THE SSTUB32868 1.8-V CONFIGURABLE REGISTERED BUFFERWITH PARITY FOR DDR2 RDIMM APPLICATIONS(From JEDEC Board Ballot JCB-07-17,
10、 formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications.The purpos
11、e is to provide a standard for the SSTUB32868 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.NOTE The designation SSTUB32868 refers to the part designation of a series of commercial logic parts common in the i
12、ndustry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.2 Device standard2.1 DescriptionThis 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDDoperation.All inputs are compatible with the JEDEC standar
13、d for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for un-terminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output.The SSTUB32868 operates from
14、 a differential clock (CK and CK). Data are registered at the crossing of CK going high and CK going low.The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and un-driven (floating) data, clock, and reference voltage (VREF) inputs are al
15、lowed. In addition, when RESET is low, all registers are reset and all outputs are forced low except QERR. The LVCMOS RESET and C inputs always must be held at a valid logic high or low level.To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in t
16、he low state during power up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register will be cleared and the data outputs will be driven low quickly
17、, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to
18、-high transition of RESET until the input receivers are fully JEDEC Standard No. 82-26Page 22 Device standard (contd)2.1 Description (contd)enabled, the design of the SSTUB32868 must ensure that the outputs will remain low, thus ensuring no glitches on the output. If the data inputs are not held low
19、, then DCS0 and DCS1 must be held high, DODT0 and DODT1, DCKE0, and DCKE1 must be held low, and all other inputs must remain stable (either low or high) for a minimum of tACT(max) after the rising edge of RESET.The SSTUB32868 includes a parity checking function. Parity, which arrives one cycle after
20、 the data input to which it applies, is checked on the PAR_IN input of the device. The corresponding QERR output signal for the data inputs is generated two clock cycles after the data, to which the QERR signal applies, is registered.The SSTUB32868 accepts a parity bit from the memory controller on
21、the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28 when C = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even pa
22、rity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state.If an error occurs and the QERR output is driven low, it stays latched low
23、for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity error duration or until RESET is driven low. If a parity error occurs on the clock cycle before the d
24、evice enters the low-power (LPM) and the QERR output is driven low, then it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1) are not included in the parity check computation.The parity er
25、ror output QERR will be reset to high by RESET transitioning low and will not be decoded until after RESET goes high and DCS0 and/or DCS1 are asserted low. CSGEN does not affect QERR operation.The C input controls the pinout configuration from register-A configuration (when low) to register-B config
26、uration (when high). The C input should not be switched during normal operation. It should be hard-wired to a valid low or high level to configure the register in the desired mode.The device also supports low-power active operation by monitoring both system chip select (DCS0 and DCS1) and CSGEN inpu
27、ts and will gate the Qn outputs from changing states when CSGEN, DCS0, and DCS1 inputs are high. If CSGEN, DCS0 or DCS1 input is low, the Qn outputs will function normally. Also, if both DCS0 and DCS1 inputs are high, the device will gate the QERR output from changing states. If either DCS0 or DCS1
28、is low, the QERR output will function normally. The RESET input has priority over the DCS0 and DCS1 control and when driven low will force the Qn outputs low, and the QERR output high. If the chip-select control functionality is not desired, then the CSGEN input can be hard-wired to ground, in which
29、 case, the setup-time requirement for DCS0 and DCS1 would be the same as for the other D data inputs. To control the low-power mode with DCS0 and DCS1 only, then the CSGEN input should be pulled up to VDDthrough a pull-up resistor.The two VREFpins (A1 and V1) are connected together internally by app
30、roximately 150 . However, it is necessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor. JEDEC Standard No. 82-26Page 32 Device standard (contd)Package options include 176-ball TFBGA (MO-246 version B).2
31、.2 176-ball TFBGA (MO-246)Figure 1 Pinout configurationNOTE 1 8 x 22 array, 6.0 x 15.0-mm body size, 0.65-mm pitch. Diagram is for reference only. See MO-246 for detailed package specification.(TOP VIEW)ABCDEFGHJKLMNPRT123456UVWYAAAB78JEDEC Standard No. 82-26Page 42 Device standard (contd)2.3 Pinout
32、 top view for 176-ball TFBGAFigure 2 1:2 Register A (C=0)NC denotes no internal connection.AD2 D1 C GND VREFGND Q1A Q1BBD4 D3 VDDVDDVDDVDDQ2A Q2BCD6(DCKE1)D5 GND GND GND GND Q3A Q3BDD8(DCKE0)D7 VDDVDDVDDVDDQ4A Q4BED9 Q6A(QCKE1A)GND GND GND GND Q5A Q5BFD10 Q8AQCKE0AVDDVDDVDDVDDQ7A Q6B(QCKE1B)GD11 Q10
33、A GND GND GND GND Q9A Q7BHD12 Q12A VDDVDDVDDVDDQ11A Q8B(QCKE0B)JDCS1 QCS1A GND GND GND GND Q10B Q9BKDCS0 QCS0A VDDVDDVDDVDDQ12B Q11BLCK CSGEN PAR_IN GND GND GND Q14B(QCS0B)Q13B(QCS1B)MCK RESET QERR VDDVDDVDDQ15B(QODT0B)Q16B(QODT1B)ND15(DODT0)Q15A(QODT0A)GND GND GND GND Q17B Q18BPD16(DODT1)Q16A(Q0DT1
34、A)VDDVDDVDDVDDQ19B Q20BRD17 Q17A GND GND GND GND Q18A Q21BTD18 Q19A VDDVDDVDDVDDQ20A Q22BUD19 Q21A GND GND GND GND Q22A Q23BVD20 Q23A VDDVDDVDDVDDQ24A Q24BWD21 D22 GND GND GND GND Q25A Q25BYD23 D24 VDDVDDVDDVDDQ26A Q26BAAD25 D26 GND GND GND GND Q27A Q27BABD27 D28 NC VDDVREFVDD Q28A Q28B12345678JEDEC
35、 Standard No. 82-26Page 52 Device standard (contd)2.3 Pinout top view for 176-ball TFBGA (contd)Figure 3 1:2 Register B (C=1)NC denotes no internal connection.AD2 D1 C GND VREFGND Q1A Q1BBD4 D3 VDDVDDVDDVDDQ2A Q2BCD6 D5 GND GND GND GND Q3A Q3BDD8 D7 VDDVDDVDDVDDQ4A Q4BED9 Q6A GND GND GND GND Q5A Q5B
36、FD10 Q8A VDDVDDVDDVDDQ7A Q6BGD11 Q10A GND GND GND GND Q9A Q7BHD12 Q12A VDDVDDVDDVDDQ11A Q8BJD13(DODT1)Q13A(QODT1A)GND GND GND GND Q10B Q9BKD14(DODT0)Q14A(QODT0A)VDDVDDVDDVDDQ12B Q11BLCK CSGEN PAR_IN GND GND GND Q14B(QODT0B)Q13B(QODT1B)MCK RESET QERR VDDVDDVDDQ15B(QCS0B)Q16B(QCS1B)ND15(DCS0)Q15A(QCS0
37、A)GND GND GND GND Q17B Q18BPD16(DCS1)Q16A(QCS1A)VDDVDDVDDVDDQ19B Q20BRD17 Q17A GND GND GND GND Q18A Q21B(QCKE0B)TD18 Q19A VDDVDDVDDVDDQ20A Q22BUD19 Q21A(QCKE0A)GND GND GND GND Q22A Q23B(QCKE1B)VD20 Q23A(QCKE1A)VDDVDDVDDVDDQ24A Q24BWD21(DCKE0)D22 GND GND GND GND Q25A Q25BYD23(DCKE1)D24 VDDVDDVDDVDDQ2
38、6A Q26BAAD25 D26 GND GND GND GND Q27A Q27BABD27 D28 NC VDDVREFVDD Q28A Q28B12345678JEDEC Standard No. 82-26Page 62 Device standard (contd)2.4 Terminal functions Data inputs = D1-D5, D7, D9-D12, D17-D28 when C=0Data inputs = D1-D12, D17-D20, D22, D24-D28 when C=1 Data outputs = Q1-Q5, Q7, Q9-Q12, Q17
39、-Q28 when C=0Data outputs = Q1-Q12, Q17-Q20, Q22, Q24-Q28 when C=1Table 1 Terminal functionsTerminalnameDescriptionElectricalcharacteristicsGND Ground Ground inputVDDPower supply voltage 1.8-V nominalVREFInput reference voltage 0.9-V nominalCK Positive master clock input Differential inputCK Negativ
40、e master clock input Differential inputC Configuration control inputs - Register A or Register B LVCMOS inputsRESETAsynchronous reset input resets registers and disables VREFdata and clock differential-input receiversLVCMOS inputCSGENChip select gate enable When high, D1-D28 inputs will be latched o
41、nly when at least one chip select input is low during the rising edge of the clock. When low, the D1-D28 inputs will be latched and re-driven on every rising edge of the clock.LVCMOS inputD1D28Data input clocked in on the crossing of the rising edge of CK and the falling edge of CKSSTL_18 inputDCS0,
42、 DCS1Chip select inputs These pins initiate DRAM address/command decodes, and as such at least one will be low when a valid address/command is present. The Register can be programmed to re-drive all D inputs (CSGEN high) only when at least one chip select input is low. If CSGEN, DCS0, and DCS1 input
43、s are high, D1D28 inputs will be disabled.SSTL_18 inputDODT0, DODT1The outputs of this register bit will not be suspended by the DC0 and DCS1 control. SSTL_18 inputDCKE0, DCKE1The outputs of this register bit will not be suspended by the DC0 and DCS1 control. SSTL_18 inputPAR_IN Parity input - arriv
44、es one clock cycle after the corresponding data input. SSTL_18 inputQ1Q28 Data outputs that are suspended by the DC0 and DCS1 control. 1.8-V CMOS outputsQCS0, QCS1 Data output that will not be suspended by the DC0 and DCS1 control. 1.8-V CMOS outputQODT0, QODT1Data output that will not be suspended
45、by the DC0 and DCS1 control. 1.8-V CMOS outputQCKE0, QCKE1Data output that will not be suspended by the DC0 and DCS1 control. 1.8-V CMOS outputQERR Output error bit - generated one clock cycle after the corresponding data output Open-drain outputNC No internal connectionJEDEC Standard No. 82-26Page
46、72 Device standard (contd)2.5 Function tableTable 2 Function table (each flip flop)Inputs OutputsRESET DCS0 DCS1 CSGEN CK CKDn, DODTn, DCKEnQn QCS0 QCS1QODT, QCKEHLL X LLLLLHLL X HHLLHH L L X L or H L or H XQ0Q0Q0Q0HLH X LLLHLHLH X HHLHHH L H X L or H L or H XQ0Q0Q0Q0HHL X LLHLLHHL X HHHLHH H L X L
47、or H L or H XQ0Q0Q0Q0HHH L LLHHLHHH L HHHHHH H H L L or H L or H XQ0Q0Q0Q0HHH H LQ0HHLHHH H HQ0HHHH H H H L or H L or H XQ0Q0Q0Q0LX or floatingX or floatingX or floatingX or floatingX or floatingX or floatingLLLLJEDEC Standard No. 82-26Page 82 Device standard (contd)2.5 Function table (contd) PAR_IN
48、 arrives one clock cycle after the data to which it applies This transition assumes QERR is high at the crossing of CK going high and CK going low. If QERR is low, it stays latched low for two clock cycles or until RESET is driven lowIf DCS0, DCS1, and CSGEN are driven high, the device is placed in
49、low-power mode (LPM). If a parity error occurs on the clock cycle before the device enters the LPM and the QERR output is driven low, it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low.Table 3 Parity and standby function tableInputs OutputRESET DCS0 DCS1 CK CK of inputs = H(D1-D28)PAR_IN QERRHLXEven L HHLXOdd L LHLX Even H LHLXOdd H HHXLEven L HHXL Odd L LHXLEven H LHXLOdd H HHHHXXQERR0H X X L or H L or H X XQERR0LX or floatingX or floatingX or floatingX or floati
