1、JEDEC STANDARD Fully Buffered DIMM Design for Test, Design for Validation (DFx) JESD82-28A (Revision of JESD82-28, February 2008) JULY 2008 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION SPECIAL DISCLAIMER: JEDEC has received information that certain patents or patent applications may be relevant to this
2、standard, and, as of the publication date of this standard, no statements regarding an assurance or refusal to license such patents or patent applications have been provided. http:/www.jedec.org/download/search/FBDIMM/Patents.xls JEDEC does not make any determination as to the validity or relevancy
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11、er of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10thStreet Suite 240 South Arlington, Virginia 22201-2107 or call (703) 907-7559 Special Disclaimer JEDEC has received information that certain patents or patent appl
12、ications may be relevant to this standard, and, as of the publication date of this standard, no statements regarding an assurance or refusal to license such patents or patent applications have been provided. http:/www.jedec.org/download/search/FBDIMM/Patents.xls JEDEC does not make any determination
13、 as to the validity or relevancy of such patents or patent applications. Prospective users of the standard should act accordingly. JEDEC Standard JESD82-28A -i- Fully Buffered DIMM Design for Test, Design for Validation (DFx) Contents 1 Scope . 1 2 Related Documents 1 3 Terms, definitions, and Abbre
14、viations 1 4 Test and Validation Overview 4 4.1 FBDIMM Overview 4 4.2 FBDIMM DFx Objectives 5 4.3 DIMM Test Process 5 4.4 Memory Manufacturing Flow. 6 4.5 Reducing Test Cost 6 4.6 Test Strategy. 6 4.7 AMB Test . 7 4.7.1 AMB Functionality and Defects. 8 4.7.2 DDR Functionality and Timing . 8 4.7.3 FB
15、DIMM Functionality and Timing 9 4.7.4 Connection of FBDIMM Pins to the Tester 9 4.7.5 FBDIMM and DDR DC Tests . 9 4.7.6 Testing DRAM Access Features 9 4.8 DIMM Test 9 4.8.1 Assembly Defects 10 4.8.2 Leakage Testing 10 4.8.3 DRAM Array Test 10 4.8.4 Programming the SPD . 10 4.8.5 FBDIMM IO Test . 10
16、4.8.6 DDR Interface Testing. 10 4.9 System Test . 10 4.10 Validation 11 5 Requirement Summary 12 5.1 DFx Requirements . 12 5.2 Required Features . 12 5.3 DFx Features and Usage 13 5.4 AMB Overview . 13 5.4.1 Memory BIST . 14 5.4.2 Interconnect BIST 15 5.5 DDR Interface Tester Compatibility . 15 5.5.
17、1 Logic Analyzer Interface . 16 5.5.2 DC Testing . 17 5.6 Host Controller Requirements. 17 6 AMB Component DFx 18 6.1 Normal Mode Debug/Validation Hooks. 18 6.2 Error Injection and In-Band Events 18 6.2.1 Decode of Southbound In-Band Debug Events. 18 6.2.2 Pattern Match on a Command . 18 6.2.3 Progr
18、ammed Event Delay . 18 6.2.4 Error Injection 18 6.2.5 Sourcing Northbound In-Band Event . 19 6.3 Logic Analyzer Interface Mode . 19 6.3.1 Link Protocol Validation/Debug . 20 6.3.2 LAI Debug Examples . 20 6.3.3 System Level Debug. 21 6.3.4 LAI Mode Architecture. 21 JEDEC Standard JESD82-28A -ii- Full
19、y Buffered DIMM Design for Test, Design for Validation (DFx) Contents (contd) 6.4 LAI Requirements 31 6.4.1 Capture all Southbound and Northbound Traffic 31 6.4.2 De-multiplex Captured FBDIMM Channel Traffic . 31 6.4.3 Drive Link Traffic with Framing Signal to Logic Analyzer. 32 6.4.4 Detection of D
20、ebug Events 32 6.4.5 Event Response Mechanisms 33 7 Common DFx Features. 34 7.1 FBDIMM IO Test . 34 7.2 Interconnect BIST 34 7.2.1 FBDIMM IBIST Architecture Specification . 34 7.2.2 Reference Architecture 43 7.2.3 Pattern Generation 47 7.2.4 Transmitter Block . 52 7.2.5 Receiver Block . 52 7.2.6 Err
21、or Detection 52 7.2.7 Validation and Test Usage Models 53 8 DIMM Test and Manufacturing 58 8.1 Transparent Mode. 58 8.1.1 Transparent Mode Architecture 60 8.1.2 Clock Frequency and Core Timing . 60 8.1.3 Edge Placement Accuracy 61 8.1.4 Transparent Mode Timing . 61 8.1.5 Error Reporting 65 8.1.6 Tra
22、nsparent Mode IO Specifications. 68 8.1.7 IO Implementation Guidelines. 68 8.2 Memory BIST . 70 8.2.1 System Level Test. 70 8.2.2 DIMM Manufacturing. 71 8.2.3 DDR Interface Testing . 71 8.2.4 MemBIST Overview . 72 8.2.5 Algorithmic Testing 77 8.2.6 DRAM Operations not Supported 79 8.2.7 Quad Rank Su
23、pport . 79 8.2.8 MemBIST Flow Control FSM 79 8.2.9 MemBIST CSFSM. 82 8.2.10 MemBIST Feature Summary . 83 8.2.11 MemBIST Registers. 84 8.2.12 MemBIST Timing Control 88 9 System Test . 93 9.1 Overview 93 9.2 Voltage Margining 93 9.3 Timing Margining. 93 9.4 Voltage, Timing Margin Support Indication 94
24、 9.5 Margin Test Usage 94 9.6 Register Definitions. 94 Annex A Revision History. 95 JEDEC Standard JESD82-28A -iii- Fully Buffered DIMM Design for Test, Design for Validation (DFx) Contents (contd) Figures Figure 4-1 Memory Channel Architecture. 4 Figure 4-2 Memory Assembly and Test Process . 6 Figu
25、re 4-3 200MHz Tester Driving 800MHz DQ 8 Figure 5-1 AMB Architecture and DFT Blocks . 14 Figure 5-2 AMB IO Loopback Methods. 15 Figure 5-3 Logic Analyzer Interface Card 17 Figure 6-1 AMB LAI Mode Signals 20 Figure 6-2 AMB LAI Mode Architecture . 22 Figure 6-3 Match and Mask Logic. 25 Figure 6-4 LAI
26、Qualification Signal Block Diagram 26 Figure 6-5 Event Signaling Timing Characteristics. 29 Figure 6-6 Event Bus Topology 29 Figure 6-7 Probing the AMB-LAI Signals. 30 Figure 7-1 Example of a Common Platform Topology for FBDIMM . 35 Figure 7-2 IBIST Loopback Operation on a Selected AMB 35 Figure 7-3
27、 IBIST Master-to-Master Mode Operation on a Selected AMB 36 Figure 7-4 FBDIMM IBIST Pattern Definition 43 Figure 7-5 AMB FBDIMM IBIST Architecture 44 Figure 7-6 AMB IBIST Instantiation Diagram 45 Figure 7-7 Pattern Generator Block Diagram . 48 Figure 7-8 Auto-Inversion Sweep Example 49 Figure 7-9 Pa
28、ttern Set 2 with Auto-Inversion Example 51 Figure 7-10 Standard IBIST Loopback Testing. 55 Figure 7-11 Master-to-Master Board Test Diagram 56 Figure 7-12 AMB External Wire Trace for Loopback Testing . 57 Figure 8-1 DRAM Architecture . 58 Figure 8-2 Transparent Mode Simplified Block Diagram 60 Figure
29、 8-3 Transparent Mode Timing . 62 Figure 8-4 Transparent Mode Write Timing . 63 Figure 8-5 Transparent Mode Read Timing . 64 Figure 8-6 BL=8 Read Timing 65 Figure 8-7 Mapping of Burst Position Bits to Error Capture . 66 Figure 8-8 Memory Address Definition, BL=4 73 Figure 8-9 Memory Address Definiti
30、on, BL=8 73 Figure 8-10 Failure Address Format 76 Figure 8-11 MemBIST Flow Control State Machine . 81 Figure 8-12 MemBIST Command State Machine 82 Figure 8-13 DRAM Write Timings (WL=2, AL=0) 88 Figure 8-14 DRAM Read Timings (CL=3, AL=0) . 89 Figure 8-15 READ - WRITE - READ Timings (CL=4, AL=0, WL=3)
31、 89 Figure 8-16 Relation Between DRAM Timing Control Parameters and MemBIST Functionality. 90 Figure 8-17 Schematic Representation of the MemBIST Read/Write Functionality. 91 Figure 8-18 Address Initialization and Sequencing During MemBIST Operation 92 JEDEC Standard JESD82-28A -iv- Fully Buffered D
32、IMM Design for Test, Design for Validation (DFx) Contents (contd) Tables Table 2-1 Related Documents 1 Table 3-1 Terms and Definitions. 2 Table 4-1 Test Overview. 7 Table 5-1 Required DFT Features 13 Table 6-1 AMB SMBus Addressing for Logic Analyzer Mode 22 Table 6-2 LAI Mode Signal and Pin Count 24
33、 Table 6-3 Local Event Pool. 27 Table 6-4 LAI Local Events. 27 Table 6-5 LAI Event Selection . 28 Table 6-6 Different Event Signal Types . 28 Table 6-7 LAI Signal Definitions3 30 Table 6-8 Setting bit 39 in Match/Mask Registers to Qualify Cmd/Data Match . 32 Table 7-1 Summary of IBIST Features 37 Ta
34、ble 7-2 AMB IBIST Modes . 39 Table 7-3 Start and End Delimiter Description4 . 42 Table 7-4 Patterns Generation Examples. 52 Table 7-5 Transmitter Block Output Select. 53 Table 8-1 Transparent Mode Pin List 62 Table 8-2 Selection of 8 Bit Data Paths When ENDOUT is Set 67 Table 8-3 Transparent Mode FB
35、DIMM Interface Signaling Specifications 68 Table 8-4 Transparent Mode Mapping 69 Table 8-5 Transparent Mode Mapping of XORA2 and XORA6 70 Table 8-6 Address Inversion . 74 Table 8-7 Refresh Programming. 77 Table 8-8 MemBIST Features. 83 Table 8-9 Memory Technology Settings 84 Table 8-10 DRAM Timing V
36、alues 84 Table 8-11 Memory Data Register 86 Table A-1 Revision History 95 JEDEC Standard JESD82-28A Page 1 Fully Buffered DIMM Design for Test, Design for Validation (DFx) (From JEDEC Board ballot, JCB-06-68 and JCB-08-30, formulated under the cognizance of the JC-40.4 Subcommittee for Digital Logic
37、 Liaison and the JC-40.5 Subcommittee on Logic Verification and Validation.) 1 Scope This FBDIMM DFx document covers Design for Test, Design for Manufacturing and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology. 2 Related Documents Table 2-
38、1 Related documents Document Revision Description FBDIMM Architecture and Protocol Specification 1.0 FBDIMM architecture and interface protocol FBDIMM Connector Specification 1.0 Connector physical parameters: pinout, footprint, mechanical drawing, and requirements FBDIMM Signaling Specification 1.0
39、 PTP link parameters: signaling, I/O, and AC and DC parameters FBDIMM AMB Specification 1.0 AMB Characteristics: pinout, package type, mechanical outline, footprint, AC/DC specs, power/thermal requirements, buffer TPT, special feature requirements (e.g., thermal sensor), requires ATE or equivalent s
40、timulus/response Required Yes Yes No Memory BIST Test DDR interface and DRAM functionality Required Yes Yes Yes Interconnect BIST Tests high speed link integrity; used during initialization Required Yes Yes Yes DDR Leakage Indirect DC leakage test of DDR interface Required No Yes Yes Error Injection
41、 Allows injection of errors to test controller/BIOS response Required Yes No Yes Logic Analyzer Mode De-serializes high speed link for analyzer or capture; needed for LAI or similar capture tools Recommended Yes No Yes Voltage Margin Transmitter drive strength settings to stress FBDIMM link Required
42、 No No Yes Timing Margin Receiver timing control allow intentional offset of data eye Recommended No No Yes 5.3 DFx Features and Usage The FBDIMM DFx features are summarized in Table 5-2. As indicated by type, the DFx features support a variety of requirements: ATE test, burn in, IO interfaces and m
43、argin testing. The major DFx features include: MemBIST for memory initialization at system power on and testing the DRAM behind the buffer Interconnect BIST, which allows testing of the high speed interconnects at system level LAI mode, which de-serializes link traffic and presents in a form usable
44、by a logic analyzer for link and protocol debug Transparent mode which allows a tester to connect to the high speed pins and send data to/from the DRAMs behind the buffer JEDEC Standard JESD82-28A Page 14 5.4 AMB Overview The major DFT blocks are the MemBIST engine and IBIST block. All DFT modes and
45、 registers are accessible from the SMBus controller. Figure 5-1 AMB Architecture and DFT Blocks 5.4.1 Memory BIST The DIMM has two primary failure mechanisms: assembly related defects and unexpected electrical behavior. Assuming DRAMs have been tested prior to assembly, there is less need to look fo
46、r cell failures, although the need will arise from time to time to support re-screening of DRAMs for issues discovered after DIMM assembly. In most cases simple patterns can verify proper connectivity between the buffer and DRAM. If there are connectivity or gross DRAM component failure the BIST eng
47、ine will be used to identify the specific failing net or DRAM to be replaced. JEDEC Standard JESD82-28A Page 15 5.4 AMB Overview (contd) 5.4.1 Memory BIST (contd) To stress electrical behavior or to facilitate failure analysis there is a need to generate patterns to isolate electrical failures or in
48、teractions. Some of this analysis will be completed in systems and some will be conducted on testers, creating a need to accommodate both methods. 5.4.2 Interconnect BIST As illustrated in Figure 5-2 there are two pattern generators and comparators: one for southbound data and one for northbound dat
49、a. The pattern generator is used to create fixed patterns during link initialization or programmable patterns for IO buffer testing. For buffer component test, the north and southbound drivers and receivers may be connected as shown. This will allow testing of the IOs with various test patterns or other conditions. There are two methods for loopback. The simplest is to connect the southbound outputs to southbound inputs and north to north. The advantage of this approach is the lane widths are balanced. The disadvantage is it may be possible to test only the resync
