1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-3BNOVEMBER 2004JEDECSTANDARDDefinition of the SSTVN16857 2.5-2.6 V 14-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and(Revision of JESD82-3A)PC3200 DDR DIMM ApplicationsNOTICE JEDEC standards and publications contain material that has been p
2、repared, reviewed, and approvedthrough the JEDEC Council level and subsequently reviewed and approved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interch
3、angeability andimprovement of products, and assisting the purchaser in selecting and obtaining with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted withou
4、t regard to whether or not their adoption mayinvolve patents or articles, materials, or processes. By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information included in JED
5、EC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments
6、, and suggestions relative to the content of this JEDEC standard or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2004 2500 Wilson Boule
7、vard Arlington, VA 22201-3834 This document may be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. Price: Please refer to the current Catalog of JEDEC Engineering Stand
8、ards and Publications or call Global Engineering Documents, USA and Canada (1-800-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced wit
9、hout permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82
10、-3BPage 1STANDARD FOR DEFINITION OF THE SSTVN16857 2.52.6-V 14-BIT SSTL_2REGISTERED BUFFER FOR DDR DIMM APPLICATIONS(From JEDEC Board Ballot JCB-04-73, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parame
11、ters, switching parameters, and test loading for definition of the SSTVN16857 14-bit SSTL_2 registered buffer for PC1600, PC2100, PC2700 and PC3200 DDR DIMM applications.The purpose is to provide a standard for the SSTVN16857 (see Note) logic device, for uniformity, multiplicity of sources, eliminat
12、ion of confusion, ease of device specification, and ease of use.NOTE The designation SSTVN16857 refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceeded by a series of manufacturer specific characters to make up a complete part de
13、signation.2 Device standard2.1 DescriptionThis 14-bit registered buffer is designed for 2.3-V to 2.7-V VDD(PC1600, PC2100, PC2700) and 2.6-V to 2.7-V VDD(PC3200) operation.All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Cla
14、ss II compatible.The SSTVN16857 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, cloc
15、k and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level.To ensure defined outputs from the register before a stable clock has been supplied
16、, RESET must be held in the low state during power up.In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will b
17、e driven low quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are
18、 low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain low.Package options include plastic thin shrink small-outline, and plastic thin very small-outline (MO-153).JEDEC St
19、andard No. 82-3BPage 22 Device standard (contd)2.2 Pinout figuresFigure 1 48-pin TSSOP package and pinout2.3 Terminal functionsTable 1 Terminal functionsTerminalnameDescriptionElectricalcharacteristicsQ1Q14 Data outputSSTL_2, Class II outputGND Ground Ground inputVDDQOutput-stage drain power voltage
20、PC1600, PC2100, PC2700 2.5-V nominalPC3200 2.6-V nominalVDDLogic power voltagePC1600, PC2100, PC2700 2.5-V nominalPC3200 2.6-V nominalRESETAsynchronous reset input resets registers and disables data and clock differential-input receiversLVCMOS inputVREFInput reference voltagePC1600, PC2100, PC2700 1
21、.25-V nominalPC3200 1.30-V nominalCK Positive master clock input Differential inputCK Negative master clock input Differential inputD1D14Data input clocked in on the crossing of the rising edge of CK and the falling edge of CKSSTL_2 input12345678910111213141516171819202122232448474645444342414039383
22、7363534333231302928272625D1D2GNDVDDD3D4D5D6D7CKCKVDDGNDVREFRESETD8D9D10D11D12VDDGNDD13D14Q1Q2GNDVDDQQ3Q4Q5GNDVDDQQ6Q7VDDQGNDQ8Q9VDDQGNDQ10Q11Q12VDDQGNDQ13Q14TOP VIEWJEDEC Standard No. 82-3BPage 32 Device standard (contd)2.4 Function table2.5 Logic diagramFigure 2 Logic diagram (positive logic)Table
23、2 Function table (each flip flop)InputsQ OutputsRESET CK CK DHLLH HHH L or H L or H XQ0LX or FloatingX or FloatingX or FloatingL1DC1R1Q13438393548RESETCKCKVREFD1To 13 Other ChannelsJEDEC Standard No. 82-3BPage 42 Device standard (contd)2.6 Absolute maximum ratingsTable 3 Absolute maximum ratings ove
24、r operating free-air temperature range (see Note 1)Supply voltage range, VDDor VDDQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 VInput voltage range, VI(See Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD+ 0.5 VOutput voltage ra
25、nge, VO(See Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDQ+ 0.5 VInput clamp current, IIK(VIVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mAOutput clamp current, IOK(VOVDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mACont
26、inuous output current, IO(VO= 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mAContinuous current through each VDD, VDDQor GND . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mAStorage temperature range, TSTG. . . . . . . . . . . . . . . . . . . . . . . . . .
27、. . . . . . . . . . . . 65 C to 150 CNOTE 1 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operati
28、ng conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2 The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.NOTE 3 This value is limited to 3.6 V maxim
29、um.2.7 Recommended operating conditionsNOTE 1 The RESET input of the device must be held at VDDor GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is low.Table 4 Recommended operating conditions (see Note 1)Min Nom Max UnitVDDSupply voltageVDDQ2.7 VVD
30、DQOutput supply voltagePC1600-2700 2.3 2.7 VPC3200 2.5 2.7 VVREFReference voltage(VREF= VDDQ/ 2)160-270151.251.35PC3200 1.25 1.30 1.35VTTTermination voltageVREF 40 mV VREFVREF+ 40 mVVVIInput voltage 0 VDDVVIHAC high-level input voltage Data inputsVREF+ 310 mVVVILAC low-level input voltage Data input
31、sVREF 310 mVVVIHDC high-level input voltage Data inputsVREF+ 150 mVVVILDC low-level input voltage Data inputs VREF 150 mV VVIHHigh-level input voltage RESET 1.7 VVILLow-level input voltage RESET 0.7 VVICRCommon-mode input range CK, CK 0.97 1.53 VVIDDifferentail input voltage CK, CK 360 mVIOHHigh-lev
32、el output current 20mAIOLLow-level output current 20TAOperating free-air temperature 0 70 CJEDEC Standard No. 82-3BPage 52 Device standard (contd)2.8 DC specificationsTable 5 Electrical characteristics over recommended operating free-air temperature range for PC1600, PC2100 and PC2700 The vendor mus
33、t supply this value for full device description.PARAMETER TEST CONDITIONSVDDMIN TYP MAX UNITVIKII= 18 mA2.3 V 1.2 VVOHIOH= 100 A 2.3 to 2.7 V VDD0.2VIOH= 16 mA2.3 V 1.95VOLIOL= 100 A2.3 to 2.7 V 0.2VIOL= 16 mA 2.3 V 0.35IIAll inputs VI= VDDor GND 2.7 V 5 AIDDStatic standby RESET = GNDIO= 02.7 V0.01m
34、AStatic operatingRESET = VDD,VI= VIH(AC)or VIL(AC)IDDDDynamic operating clock onlyRESET = VDD,VI= VIH(AC)or VIL(AC),CK and CK switching 50% duty cycleIO= 02.7 VA/clock MHzDynamic operating per each data inputRESET = VDD,VI= VIH(AC)or VIL(AC),CK and CK switching 50% duty cycle. One data input switchi
35、ng at half clock frequency, 50% duty cycle.A/clock MHz/data inputrOHOutput high IOH= -20 mA 2.3 to 2.7 V 7 20rOLOutput lowIOL= 20 mA2.3 to 2.7 V 7 20 rO()|rOH- rOL| each separate bitIO= 20 mA, TA= 25 C2.5 V 4 CiData inputsVI= VREF 310 mV2.5 V2.5 3.5pFCK and CK VICR= 1.25 V, VI(PP)= 360 mV 2.5 3.5RES
36、ETVI= VDDor GNDJEDEC Standard No. 82-3BPage 62 Device standard (contd)2.8 DC specifications (contd)Table 6 Electrical characteristics over recommended operating free-air temperature range for PC3200The vendor must supply this value for full device description.PARAMETER TEST CONDITIONS VDDMIN TYP MAX
37、 UNITVIKII= 18 mA 2.5 V 1.2 VVOHIOH= 100 A2.5 to 2.7 VVDD0.2VIOH= 16 mA2.5 V 1.95VOLIOL= 100 A 2.5 to 2.7 V 0.2VIOL= 16 mA2.5 V 0.35IIAll inputsVI= VDDor GND2.7 V 5 AIDDStatic standby RESET = GNDIO= 0 2.7 V0.01mAStatic operatingRESET = VDD,VI= VIH(AC)or VIL(AC)IDDDDynamic operating clock onlyRESET =
38、 VDD,VI= VIH(AC)or VIL(AC),CK and CK switching 50% duty cycleIO= 02.7 VA/clock MHzDynamic operating per each data inputRESET = VDD,VI= VIH(AC)or VIL(AC),CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle.A/clock MHz/data inputrOHOutput highIOH= -20 m
39、A2.5 to 2.7 V 7 20 rOLOutput low IOL= 20 mA 2.5 to 2.7 V 7 20rO()|rOH- rOL| each separate bitIO= 20 mA, TA= 25 C 2.6 V 4CiData inputs VI= VREF 310 mV2.6 V2.5 3.5pFCK and CKVICR= 1.30 V, VI(PP)= 360 mV2.5 3.5RESETVI= VDDor GNDJEDEC Standard No. 82-3BPage 72 Device standard (contd)2.9 Timing requireme
40、ntsThis parameter is not necessarily production tested.NOTE 1 Data inputs must be low a minimum time of tactmax, after RESET is taken highNOTE 2 Data and clock inputs must be held at valid levels (not floating) a minimum time of tinactmax, after RESET is taken low.NOTE 3 For data signal input slew r
41、ate 1 V/ns.NOTE 4 For data signal input slew rate 0.5 V/ns and 1 V/ns.NOTE 5 CK, CK signals input slew rates are 1 V/ns.Table 7 Timing requirements over recommended operating free-air temperature range.PC1600, PC2100, PC2700PC3200UNITVDD= 2.5 V 0.2 V VDD= 2.6 V 0.1 VMIN MAX MIN MAXfclockClock freque
42、ncy 200 220 MHztwPulse duration, CK, CK high or low 2.5 2.5 nstactDifferential inputs active time (see Note 1)22 22 nstinactDifferential inputs inactive time (see Note 2)22 22 nstsuSetup time, fast slew rate (See Notes 3 and 5)Data before CK , CK 0.65 0.65 nsSetup time, slow slew rate (See Notes 4 a
43、nd 5)0.9 0.75 nsthHold time, fast slew rate (See Notes 3 and 5)Data after CK , CK 0.75 0.75 nsHold time, slow slew rate (See Notes 4 and 5)0.9 0.9 nsJEDEC Standard No. 82-3BPage 82 Device standard (contd)2.10 AC specificationsNOTE 2 Measured with reference load, see Figure 4. tPDMis vendor specific.
44、 It is not required for compliant devices that this parameter is specified.NOTE 3 The Simultaneous Switching specification is guaranteed by Characterization. NOTE 4 Measured with reference load, see Figure 4. tPDMis vendor specific. It is not required for compliant devices that this parameter is spe
45、cified.Table 8 Switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)PARAMETERFROM(INPUT)TO(OUTPUT)PC1600, PC2100, PC2700UNITVDD= 2.5 V 0.2 VMIN MAXfmax200 MHztpdCK and CK Q1.12.8nstPHLRESET Q5tPDMCK - CK QT see Note 1 nsTable 9 Switch
46、ing characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)PARAMETERFROM(INPUT)TO(OUTPUT)PC3200UNITVDD= 2.6 V 0.1 VMIN MAXfmax220 MHztpdCK and CK Q1.12.4nstpdss (see Note 1)CK and CK Q27tPHLRESET Q5tPDMCK - CK QT see Note 2 nsJEDEC Standard No. 8
47、2-3BPage 93 Output buffer characteristics3.1 Voltage vs. current (V/I)The following table describes output-buffer Voltage vs. Current (V/I) characteristics that are sufficient to meet the requirements of registered DDR DIMM performance and timings. These characteristics are not necessarily productio
48、n tested but can be guaranteed by design or characterization. Compliance with these curves is not mandatory if it can be adequately demonstrated that alternate characteristics meet the requirements of the registered DDR DIMM application.Table 10 Output buffer voltage vs. current (V/I) characteristic
49、sVoltage(V)Pull-down Pull-dpI(mA) I(mA) I(mA) I(mA)MIN MAX MIN MAX0000-00.1 5 18 -5 -180.2 10 30 -10 -300.3 15 44 -15 -440.4 19 55 -19 -550.5 23 67 -23 -670.6 27 78 -27 -780.7 30 90 -30 -900.8 34 101 -34 -980.9 36 112 -36 -1061.0 38 121 -38 -1131.1 40 131 -40 -1191.2 42 140 -42 -1251.3 43 150 -43 -1301.4 44 159 -44 -1341.5 44 167 -44 -1371.6 45 176 -45 -1401.7 45 184 -45 -1431.8 45 192 -45 -1461.9 45 199 -45 -1492.0 45 206 -45 -1522.1 46 212 -46 -1542.2 46
