1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-4BMAY 2003JEDECSTANDARDDefinition of the SSTV16859 2.5 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for Stacked DDR DIMM Applications (Revision of JESD82-4A)NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and ap
2、provedthrough the JEDEC Council level and subsequently reviewed and approved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovemen
3、t of products, and assisting the purchaser in selecting and obtaining with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted without regard to whether or no
4、t their adoption mayinvolve patents or articles, materials, or processes. By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information included in JEDEC standards and publicat
5、ions represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and suggestions relativ
6、e to the content of this JEDEC standard or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2003 2500 Wilson Boulevard Arlington, VA 22201-
7、3834 This document may be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or
8、call Global Engineering Documents, USA and Canada (1-800-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organiza
9、tions may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-4BPage 1STANDARD FOR DEF
10、INITION OF THE SSTV16859 2.5-V 13-BIT TO 26-BIT SSTL_2REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS(From JEDEC Board Ballots JCB-02-136, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, swi
11、tching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications.The purpose is to provide a standard for the SSTV16859 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of d
12、evice specification, and ease of use.NOTE The designation SSTV16859 refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer-specific characters to make up a complete part designation.2 Device standard2.
13、1 DescriptionThis 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VDDoperation.All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.The SSTV16859 operates from a differential clock (CK and C
14、K). Data are registered at the crossing of CK going high, and CK going low.The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET i
15、s low all registers are reset, and all outputs are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level.To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.In the DDR DIMM applic
16、ation, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input
17、 receivers, thus ensuring no glitches on the output. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transitio
18、n of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain low.Package options include plastic thin shrink small-outline package (MO-153).JEDEC Standard No. 82-4BPage 22 Device standard (contd)2.2 Pinout figureFigure 1 64-Pin dual inline package pinou
19、t123456789101112131415161718192021222324646362616059585756555453525150494847464544434241VDDQGNDD13VDDVDDQGNDD11D10D9GNDD7VDDQVDDVREFGNDD5D4Q13AQ12AQ9AVDDQGNDTOP VIEW25262728293031324039383736353433D12D8RESETGNDCKCKD6D3GNDVDDQVDDD2D1GNDVDDQQ11AQ10AQ8AQ7AQ6AQ5AQ4AQ3AQ2AGNDQ1AQ13BVDDQQ12BQ11BQ10BQ9BQ8B
20、Q7BQ6BGNDVDDQQ5BQ4BQ3BQ2BQ1BJEDEC Standard No. 82-4BPage 32 Device standard (contd)Figure 2 56-Pin (MO#220, variation VLLD2, E2 = 5.2mm nominal, D2 = 4.5mm nominal) Package Pinout2.3 Terminal functionsTable 1 Terminal functionsTerminalnameDescriptionElectricalcharacteristicsQ1Q13 Data outputSSTL_2,
21、Class II outputGND Ground Ground inputVDDQOutput-stage drain power voltage 2.5-V nominalVDDLogic power voltage 2.5-V nominalRESETAsynchronous reset input resets registers and disables data and clock differential-input receiversLVCMOS inputVREFInput reference voltage 1.25-V nominalCK Positive master
22、clock input Differential inputCK Negative master clock input Differential inputD1D13Data input clocked in on the crossing of the rising edge of CK and the falling edge of CKSSTL_2 inputQ7AQ6AQ5AQ4AQ3AQ2AQ1AQ13BVDDQQ12BQ11BQ10BQ9BQ8B114152829434256D10D9D8D7RESET#GNDCLK#CLKVDDQVDDVREFD6D5D4Q8A VDDQ Q9
23、A Q10A Q11A Q12A Q13A VDDQ GND D13 D12 VDD VDDQ D11Q7B Q6BVDDQQ5B Q4B Q3B Q2B Q1BVDDQD1 D2VDDVDDQD3GNDJEDEC Standard No. 82-4BPage 42 Device standard (contd)2.4 Function table2.5 Logic diagramFigure 3 Logic diagram (positive logic)Table 2 Function table (each flip flop)InputsQ OutputsRESET CK CK DHL
24、LH HHH L or H L or H XQ0LX or FloatingX or FloatingX or FloatingL1DC1R16Q1A5148494535RESETCKCKVREFD1To 12 Other Channels32Q1BJEDEC Standard No. 82-4BPage 52 Device standard (contd)2.6 Absolute maximum ratingsTable 3 Absolute maximum ratings over operating free-air temperature range (see Note 1)Suppl
25、y voltage range, VDDor VDDQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 VInput voltage range, VI(See Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to VDD+ 0.5 VOutput voltage range, VO(See Notes 2 and 3) . . . . . . . . . . . . . .
26、 . . . . . . . . 0.5 V to VDDQ+ 0.5 VInput clamp current, IIK(VIVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mAOutput clamp current, IOK(VOVDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous output current, IO(VO= 0 to VDDQ) . . . . . . .
27、 . . . . . . . . . . . . . . . . . . . . . . . . . .50 mAContinuous current through each VDD, VDDQor GND . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mAStorage temperature range, TSTG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C to 150 CNOTE 1 Stresses b
28、eyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-ma
29、ximum-rated conditions for extended periods may affect device reliability. NOTE 2 The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.NOTE 3 This value is limited to 3.6 V maximum.2.7 Recommended operating conditionsNOTE The RESET
30、input of the device must be held at VDDor GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is low.Table 4 Recommended operating conditions (see Note)Min Nom Max UnitVDDSupply voltageVDDQ2.7 VVDDQOutput supply voltage 2.3 2.7 VVREFReference voltage (VR
31、EF= VDDQ/ 2)1.15 1.25 1.35 VVTTTermination voltageVREF 40 mV VREFVREF+ 40 mVVVIInput voltage 0 VDDVVIHAC high-level input voltage Data inputsVREF+ 310 mVVVILAC low-level input voltage Data inputsVREF 310 mVVVIHDC high-level input voltage Data inputsVREF+ 150 mVVVILDC low-level input voltage Data inp
32、uts VREF 150 mV VVIHHigh-level input voltage RESET 1.7 VVILLow-level input voltage RESET 0.7 VVICRCommon-mode input range CK, CK 0.97 1.53 VVIDDifferentail input voltage CK, CK 360 mVIOHHigh-level output current 20mAIOLLow-level output current 20TAOperating free-air temperature 0 70 CJEDEC Standard
33、No. 82-4BPage 62 Device standard (contd)2.8 DC specificationsTable 5 Electrical characteristics over recommended operating free-air temperature rangePARAMETER TEST CONDITIONSVDDMIN TYP MAX UNITVIKII= 18 mA2.3 V 1.2 VVOHIOH= 100 A2.3 to 2.7 VVDD0.2VIOH= 16 mA 2.3 V 1.95VOLIOL= 100 A2.3 to 2.7 V 0.2VI
34、OL= 16 mA2.3 V 0.35IIAll inputsVI= VDDor GND2.7 V 5 AIDDStatic standby RESET= GNDIO= 02.7 V0.01mAStatic operatingRESET = VDD,VI= VIH(AC)or VIL(AC)IDDDDynamic operating clock onlyRESET = VDD,VI= VIH(AC)or VIL(AC),CK and CK switching 50% duty cycleIO= 0 2.7 VA/clock MHzDynamic operating per each data
35、inputRESET = VDD,VI= VIH(AC)or VIL(AC),CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle.A/clock MHz/data inputrOHOutput highIOH= -20 mA2.3 to 2.7 V 7 20 rOLOutput lowIOL= 20 mA2.3 to 2.7 V 7 20 rO()|rOH- rOL| each separate bitIO= 20 mA, TA= 25 C 2.
36、5 V 4CiData inputsVI= VREF 310 mV2.5 V2.5 3.5pFCK and CKVICR= 1.25 V, VI(PP)= 360 mV2.5 3.5RESET VI= VDDor GND The vendor must supply this value for full device description.JEDEC Standard No. 82-4BPage 72 Device standard (contd)2.9 Timing requirementsNOTE 1 Data inputs must be low a minimum time of
37、tactmax, after RESET is taken highNOTE 2 Data and clock inputs must be held at valid levels (not floating) a minimum time of tinactmax, after RESET is taken low.NOTE 3 For data signal input slew rate 1 V/ns.NOTE 4 For data signal input slew rate 0.5 V/ns and 1 V/ns.NOTE 5 CK, CK signals input slew r
38、ates are 1 V/ns.2.10 AC specificationsNOTE Measured with reference load, see Figure 4. tPDMis vendor specific. It is not required for compliant devices that this parameter is specified.Table 6 Timing requirements over recommended operating free-air temperature range.VDD= 2.5 V 0.2 VUNITMIN MAXfclock
39、Clock frequency 200 MHztwPulse duration, CK, CK high or low 2.5 nstactDifferential inputs active time (see Note 1) 22 nstinactDifferential inputs inactive time (see Note 2) 22 nstsuSetup time, fast slew rate (See Notes 3 and 5)Data before CK , CK 0.75nsSetup time, slow slew rate (See Notes 4 and 5)
40、0.9thHold time, fast slew rate (See Notes 3 and 5)Data after CK , CK 0.75nsHold time, slow slew rate (See Notes 4 and 5) 0.9This parameter is not necessarily production tested.Table 7 Switching characteristics over recommended operating free-air temperature range(unless otherwise noted) (see Figure
41、3)PARAMETERFROM(INPUT)TO(OUTPUT)VDD= 2.5 V 0.2 VUNITMIN MAXfmax200 MHztpdCK and CK Q1.12.8nstPHLRESET Q5tPDMCK - CK QT see Note nsJEDEC Standard No. 82-4BPage 83 Output buffer characteristics3.1 Voltage vs. current (V/I)The following table describes output-buffer Voltage vs. Current (V/I) characteri
42、stics that are sufficient to meet the requirements of registered DDR DIMM performance and timings. These characteristics are not necessarily production tested but can be guaranteed by design or characterization. Compliance with these curves is not mandatory if it can be adequately demonstrated that
43、alternative characteristics meet the requirements of the registered DDR DIMM application.Table 8 Output buffer voltage vs. current (V/I) characteristicsVoltage(V)Pull-down Pull-dpI(mA) I(mA) I(mA) I(mA)MIN MAX MIN MAX0000-00.1 5 18 -5 -180.2 10 30 -10 -300.3 15 44 -15 -440.4 19 55 -19 -550.5 23 67 -
44、23 -670.6 27 78 -27 -780.7 30 90 -30 -900.8 34 101 -34 -980.9 36 112 -36 -1061.0 38 121 -38 -1131.1 40 131 -40 -1191.2 42 140 -42 -1251.3 43 150 -43 -1301.4 44 159 -44 -1341.5 44 167 -44 -1371.6 45 176 -45 -1401.7 45 184 -45 -1431.8 45 192 -45 -1461.9 45 199 -45 -1492.0 45 206 -45 -1522.1 46 212 -46
45、 -1542.2 46 218 -46 -1562.3 46 222 -46 -1572.4 46 226 -46 -1592.5 46 229 -46 -1602.6 46 233 -46 -1612.7 46 234 -46 -162JEDEC Standard No. 82-4BPage 93 Output buffer characteristics (contd)3.2 Slew rateThe following table describes output-buffer slew-rate characteristics that are sufficient to meet t
46、he requirements of registered DDR DIMM performance and timings. These characteristics are not necessarily production tested but can be guaranteed by design or characterization. Compliance with these rates is not mandatory if it can be adequately demonstrated that alternative characteristics meet the
47、 requirements of the registered DDR DIMM application. This information does not necessarily have to appear in the device datasheet.Obtain rise and fall time measurements by using the same procedure for obtaining “Ramp” data according to the current EIA IBIS specification. In particular it is very im
48、portant to note that the following slew rates are specified at the output of the die, without package parasitics in the power, ground or output paths. The measurement points are at 20% and 80%. The slew-rate test load shall be a 50 resistor to GND for Rise, and a 50 resistor to VDDQfor Fall. The dV/
49、dt ratio is reduced to V/ns.:3.3 Simultaneous switchingThe vendor must supply, as requested, simultaneous switching information for full device description. In particular, slow corner propagation-delay increase due to simultaneous switching conditions is necessary for post-register timing analysis. This information does not necessarily have to appear in the device datasheet.Table 9 Output-buffer slew rate characteristicsdV/dt Min MaxRise 1.1 V/ns 13.9V/nsFall 1.1 V/ns 14.5 V/nsJED
