1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-8.01FEBRUARY 2004JEDECSTANDARDStandard for Definition of CU877 PLLClock Driver for Registered DDR2 DIMM Applications(Minor Revision of JESD82-8, July 2003)NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and app
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9、ited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-8.01Page 1STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVERFOR REGISTE
10、RED DDR2 DIMM APPLICATIONS(Formerly JEDEC Board Ballot JCB-02-105, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CU877 PLL clock devi
11、ce for registered DDR2 DIMM applications.The purpose is to provide a standard for a CU877 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. 2 Definitions for the purpose of this documentCI() Delta input capacitance.3 D
12、evice standard3.1 DescriptionThis PLL Clock Buffer is designed for a VDDQ of 1.8 V, an AVDDof 1.8 V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.The device is a zero delay buffer that distributes a differential clock input pair (CK,
13、CK) to ten differential pair of clock outputs (Y0:9, Y0:9) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS (OE, OS) and the Analog Power input (AVDD). When OE is low, the outp
14、uts (except FBOUT/FBOUT) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on Y7/Y7 (they are free running in
15、addition to FBOUT/FBOUT). When AVDDis grounded, the PLL is turned off and bypassed for test purposes.When both clock signals (CK, CK) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect th
16、e logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between t
17、he feedback clock pair (FBIN, FBIN) and the input clock pair (CK, CK) within the specified stabilization time tL.The PLL in the CU877 clock driver uses the input clocks (CK, CK) and the feedback clocks (FBIN, FBIN) to provide high-performance, low-skew, low-jitter output differential clocks (Y0:9, Y
18、0:9). The CU877 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.The CU877 is characterized for operation from 0oC to 70 oC.JEDEC Standard No. 82-8.01Page 23.1 Description (contd)TopviewFigure 1 52-Ball VF-BGA (10x6 Array, 7.0x4.5 mm Body Size, 0.65 mm Pitch, MO-225 Variation BA)
19、 package pinoutsFigure 2 40-pin HP-VFQFP-N (6.0x6.0 mm Body Size, 0.5 mm Pitch, MO-220, variation VJJD-2, E2 & D2 nominal = 2.9 mm +/- 0.15 mm) package pinoutsGND GND GND Y6Y2 GND NB NB GND Y7Y2 VDDQ VDDQ OS Y7CK NB NB FbinVDDQ NB NB OE FbinVDDQ VDDQ VDDQ VDDQ FboutAVDD GND GND FboutGND GNDY1VDDQVDD
20、QCKAGNDGNDY3NBNBY8Y6Y1 Y0 Y5 Y5Y0612 453CDEHBFGJAY3K Y4 Y9 Y9 Y8Y4BGAVDDQGNDGNDMLFVDDQ1234567891011 12 13 14 15 16 17 18 19 202122232440 39 38 37 36 35 34 33 32 31302928272625 FBOUTVDDQFBINFBINY7Y9 Y8 Y8FBOUTY7Y6Y6Y1VDDQY9VDDQGNDY5Y5Y0 Y0AVDDVDDQAGNDCKY2Y2Y3Y3 Y4Y4CKVDDQVDDQOSOEY1GNDVDDQVDDQJEDEC St
21、andard No. 82-8.01Page 33.2 Terminal functions3.3 Function table* L(Z)means the outputs are disabled to a low state meeting the IODLlimit in Table 5.Table 1 Terminal FunctionsTerminalNameDescriptionElectricalCharacteristicsAGND Analog Ground GroundAVDDAnalog power 1.8 V nominalCKClock input with a (
22、10K-100K Ohm) pulldown resistor Differential inputCK Complementary clock input with a (10K-100K Ohm) pulldown resistor Differential inputFBIN Feedback clock input Differential inputFBIN Complementary feedback clock input Differential inputFBOUT Feedback clock output Differential outputFBOUT Compleme
23、ntary feedback clock output Differential outputOE Output Enable (Asynch) LVCMOS inputOSOutput Select (tied to GND or VDDQ)LVCMOS inputGND Ground GroundVDDQLogic and output power 1.8 V nominalY0:9 Clock outputs Differential outputsY0:9 Complementary clock outputs Differential outputsNB No ballTable 2
24、 Function tableInputs OutputsPLLAVDDOE OS CK CK YYFBOUT FBOUTGND H X L H L LHBypassed/OffGND H X H L HL LBypassed/OffGND L H L H *L(Z)*L(Z) LHBypassed/OffGND L L H L*L(Z),Y7 active*L(Z),Y7 activeHLBypassed/Off1.8V(nom) LHLH*L(Z)*L(Z) LHOn1.8V(nom) LLHL*L(Z),Y7 active*L(Z),Y7 activeHL On1.8V(nom) HXL
25、HLHLHOn1.8V(nom) H X H L HLHL On1.8V(nom) XXLL*L(Z)*L(Z)*L(Z)*L(Z)Off1.8V(nom) XXHH ResrvedJEDEC Standard No. 82-8.01Page 43.4 Logic diagramFigure 3 Logic diagram (positive logic)Y8Y8Y7Y7Y6Y6Y5Y5Y4Y4Y3Y3Y2Y2Y1Y1Y0Y0Y9Y9FBOUTFBOUTPowerdownControl andTest LogicAVDDCKFBINCKFBINPLLOELD* or OEPLL bypassL
26、D*LD*, OS or OEOS* The Logic Detect (LD) powers down the device when alogic low is applied to both CK and CK.GND10K-100kJEDEC Standard No. 82-8.01Page 53.5 Absolute maximum ratingsTable 3 Absolute maximum ratings over operating free-air temperature range (see Note 1)Supply voltage range, VDDQor AVDD
27、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 2.5 VInput voltage range, VI(see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to VDDQ+ 0.5 VOutput voltage range, VO(see Notes 2 and 3). . . . . . . . . . . . . . .
28、. . . . . . . . . . . . . . . . 0.5 V to VDDQ+ 0.5 VInput clamp current, IIK(VIVDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAOutput clamp current, IOK(VOVDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous ou
29、tput current, IO(VO= 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous current through each VDDQor GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mAStorage temperature range, TSTG. . . . . . . . . . .
30、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C to 150 CNOTE 1 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other cond
31、itions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2 The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are obser
32、ved.NOTE 3 This value is limited to 2.5 V maximum.3.6 Recommended operating conditionsNOTE 1 The PLL is turned off and bypassed for test purposes when AVDDis grounded. During this test mode, VDDQremains within the recommended operationing conditions and no timing parameters are guaranteed.NOTE 2 VID
33、is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 12 for definition. For CK and CK the VIHand VILlimits are used to define the DC low and high levels for the logic detect state. Table 4 Recommended operating conditions (see Note 1)Min Nom Max Unit
34、VDDQOutput supply voltage 1.7 1.8 1.9 VAVDDSupply voltage See Note 1VDDQVILLow-level input voltage, see Note 2OE, OS, CK, CK0.35 x VDDQVVIHHigh-level input voltage, see Note 2OE, OS, CK, CK0.65 x VDDQVIOHHigh-level output current, See Figure 5 - 9 mAIOLLow-level output current, See Figure 5 9 mAVIXI
35、nput differential-pair cross voltage(VDDQ/2)-0.15 (VDDQ/2)+0.15VVINInput voltage level - 0.3VDDQ+ 0.3VVIDInput differential voltage,See Note 2 and Figure 12DC 0.3 VDDQ+ 0.4 VAC 0.6VDDQ+ 0.4VTAOperating free-air temperature 0 70 CJEDEC Standard No. 82-8.01Page 63.7 DC specificationsNOTE 1 Total IDD=
36、IDDQ+IADD= FCK* CPD* VDDQ, solving for CPD= (IDDQ+IADD)/(FCK*VDDQ) where FCKis the input Frequency, VDDQis the power supply and CPDis the Power Dissipation Capacitance.Table 5 Electrical characteristics over recommended operating free-air temperature rangePARAMETER TEST CONDITIONSAVDD, VDDQMIN TYP M
37、AX UNITVIKAll inputs II= 18 mA1.7 V -1.2 VVOHHigh output voltageIOH= 100 A1.7 to 1.9 VVDDQ-0.2VIOH= 9 mA 1.7 V 1.1VOLLow output voltageIOL= 100 A1.7 to 1.9 V 0.1VIOL= 9 mA1.7 V 0.6IODLOutput disabled low currentOE = L, VODL= 100mV 1.7 V 100 AVODOutput differential voltage, the magnitude of the diffe
38、rence between the true and complimentary outputs, see Figure 12 for definition.1.7 V 0.6 VIICK, CK VI= VDDQor GND 1.9 V 250AOE, OS, FBIN, FBINVI= VDDQor GND1.9 V 10IDDLDStatic supply current, IDDQ+ IADDCK and CK = L 1.9 V 500 AIDDDynamic supply current,IDDQ+ IADD, see Note 1 for CPDcalculationCK and
39、 CK = 270 MHz,all outputs are open (not connected to a PCB)1.9 V 300 mACICK and CK VI= VDDQor GND1.8 V23pFFBIN and FBINVI= VDDQor GNDCI()CK and CKVI= VDDQor GND0.25FBIN and FBIN VI= VDDQor GND 0.25JEDEC Standard No. 82-8.01Page 73.8 Timing requirementsNOTE 1 The PLL must be able to handle spread spe
40、ctrum induced skew.NOTE 2 Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.)NOTE 3 Application clock frequency indicates a range over which the PLL must meet all
41、timing parameters.NOTE 4 Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase
42、 lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. Table 6 Timing requirements over recommended opera
43、ting free-air temperature range.AVDD, VDDQ= 1.8 V 0.1 VUNITMIN MAXfCKOperating clock frequency (see Notes 1 and 2) 125 270 MHzApplication clock frequency (see Notes 1 and 3) 160 270 MHztDCInput clock duty cycle 40 60 %tLStabilization time (see Note 4) 15 sJEDEC Standard No. 82-8.01Page 83.9 AC speci
44、ficationsNOTE 1 Static Phase Offset does not include Jitter.NOTE 2 Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.NOTE 3 The Output Slew Rate is determined from the IBIS model into the load shown in Figure 4. It is measure
45、d single ended.NOTE 4 Design Target is 60ps, unless it is unacheivable.NOTE 5 VOXspecified at the DRAM clock input or the test load.NOTE 6 To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK,CK and Feedback Clock Input FBIN, FBIN are r
46、ecommended to be nearly equal. The 2.5 V/ns slew rates are shown as a recommended target. Compliance with these Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2 DIMM application. NOTE 7 There are two differ
47、ent terminations that are used with the above ac tests. The load/board in Figure 5 is used to measure the input and output differential-pair cross-voltage only. The load/board in Figure 6 is used to measure all other tests. For consistency, equal length cables should be used.Table 7 Switching charac
48、teristics over recommended operating free-air temperature range(unless otherwise noted) (see Note 7)PARAMETER DESCRIPTION DiagramAVDD, VDDQ= 1.8 V 0.1 VUNITMIN Nom MAXtenOE to any Y/Y see Figure 14 8 nstdisOE to any Y/Y see Figure 14 8 nstjit(cc+)Cycle-to-cycle period jitter see Figure 7040ptjit(cc-
49、) 0 -40 pst()Static phase offset (see Note 1) see Figure 8 -50 50 pst()dynDynamic phase offset see Figure 13 -50 50 pstsk(o) Output clock skew see Figure 9 40 pstjit(per) Period jitter (see Note 2) see Figure 10 -40 40 pstjit(hper) Half-period jitter (see Note 2, 4) see Figure 11 -75 75 psslr(i)Output Enable (OE) see Figure 12 0.5 V/nsInput clock slew rate, measured single ended.see Figure 12 1 2.5 4 V/nsslr(o)Output clock slew rate, measured single ended. (see Note 3, 6)see Figures 4 and 121.5 2.5 3 V/nsVOXOutput di
