1、 JEDEC STANDARD A Procedure for Measuring P-Channel MOSFET Negative Bias Temperature Instabilities JESD90 NOVEMBER 2004 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Director
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9、s may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 90 -i- Introduction Negative Bi
10、as Temperature Instabilities (NBTI) experienced by p-channel MOSFETs over time are an important reliability concern in modern microcircuits. The physical nature of the NBTI damage is not completely understood. It is believed that the NBTI damage is controlled by an electro-chemical reaction where ho
11、les in the P-MOSFET inverted channel interact with Si compounds (Si-H, Si-D, etc) at the Si-SiO2 interface to produce donor type interface states and possibly positive fixed charge. The relative contribution of interface states generation and positive fixed charge formation is very sensitive to the
12、gate oxide process used in the technology. The electro-chemical reaction is strongly dependent on the gate vertical electric field and the temperature at stress. For this reason it is necessary to use the minimum oxide thickness allowed in the technology. The interface states generation and positive
13、 fixed charge formation may lead to substantial P-MOSFET parameter changes, in particular to an increase of threshold voltage (VT). VT is the most commonly used device parameter (as compared to transconductance or any drain current) to track the P-MOSFET degradation. This failure mechanism, which is
14、 found to be strongly thermally activated, may seriously affect the PMOS device reliability, particularly for analog blocks/designs where matching issues can be critical. The material contained in this publication was formulated under the cognizance of the JEDEC JC-14.2 Subcommittee. JEDEC Standard
15、No. 90 -ii- JEDEC Standard No. 90 Page 1 A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES (From JEDEC Board ballot JCB-04-47, formulated under the cognizance of the JC-14.2.2, Device Reliability Working Group.) 1 Scope This document describes an accelerated stress a
16、nd test methodology for measuring device parameter changes of a single p-channel MOSFET after Negative Bias Temperature Instability (NBTI) stress at dc bias conditions. This document gives a procedure to investigate NBTI stress in a symmetric voltage condition with the channel inverted (VGS 0) and n
17、o channel conduction (VDS = 0).There can be NBTI degradation during channel conduction (VGS 0, VDS 0), however, this document does not cover this phenomena. Typically, p-channel MOSFET devices will display maximum parameter changes at elevated temperatures. The purpose of this document is to specify
18、 a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transi
19、stor manufacturing process. The device parameters shift criteria specified in this document are to be used for comparison purposes only and should not be used as acceptance or rejection criteria. It is also important to realize that this procedure should not be interpreted as a means of predicting M
20、OS IC failure rates. The impact of the p-channel MOSFET change on actual circuit performance is not addressed in this document. Though this procedure was developed for wafer level stressing, it is also applicable to packaged structures. 2 Applicable standards ASTM F616-86, Standard Method for Measur
21、ing MOSFET Drain Leakage Current. ASTM F617-86, Standard Method for Measuring MOSFET Linear Threshold Voltage. ASTM F1096-87, Standard Method for Measuring MOSFET Saturated Threshold Voltage. JESD77A, Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices. JESD6
22、0A, A Procedure for Measuring P-Channel MOSFET Hot-Carrier Induced Degradation at Maximum Gate CurrentUnder DC Stress. JESD28, A Procedure for Measuring N-Channel MOSFET Hot-Carrier Induced Degradation Under DC Stress. JEDEC Standard No. 90 Page 2 3 Terms and definitions bulk current, dc (IB): The d
23、irect current into the bulk contact, which is the n-well current of a P-MOSFET. bulk-source voltage (VBS): The bulk-to-source voltage. constant-current threshold voltage (VT(ci): The gate-source voltage at which the drain current is equal to a constant current, appropriate for a given P-MOSFET techn
24、ology, times the ratio of gate width (W) to gate length (L). VT(ci) can be calculated using = LWIIat VV DoDGST(ci) (1) where: W and L are the gate width and gate length as printed on the wafer; IDo is typically 0.025 A but another value may be selected for a given technology such that VT(ci) is in t
25、he subthreshold region of the device. NOTE 1 The measurement technique must determine VT(ci) to within a 1-mV resolution. If the VGS step size is larger than 1 mV, then a linear interpolation method may be used to achieve the 1-mV resolution. NOTE 2 Typical dc bias voltages for the linear VT(ci) mea
26、surements are VDS = VDS(lin), VBS = VBB. For the saturation VT(ci) the measurements conditions are VDS = -VDD and VBS = VBB. drain current, dc (ID): The direct current into the drain contact. drain leakage current (ID(leak): The drain current when the transistor is biased in its off state. NOTE 1 ID
27、(leak) may have contributions from channel off-state current, gate-induced drain leakage (GIDL), and drain-to-gate tunneling currents. NOTE 2 Typical bias voltages for ID(leak) measurements are VDS = -VDD and VGS = VBS = VBB. drain-source voltage (VDS): The drain-to-source voltage. extrapolated thre
28、shold voltage (VT(ext): The threshold voltage extrapolated from measurement of maximum slope (gm(max) of the ID-VGS curve, as described in ASTM F617-86. VT(ext) can be calculated using V V (g ) I (g )gT(ext) GS m(max) D m(max)m(max)= - (2) where: VGS(gm(max) is the gate voltage at the point of the m
29、aximum slope of the ID-VGS curve; ID(gm(max) is the drain current at the point of the maximum slope of the ID-VGS curve; gm(max) is the maximum slope of the ID-VGS curve in the linear region. NOTE The bias voltages for VT(ext) measurements are VDS = VDS(lin) and VBS = VBB. JEDEC Standard No. 90 Page
30、 3 3 Terms and definitions (contd) gate current, dc (IG): The direct current into the gate contact. gate-source voltage (VGS): The gate-to-source voltage. linear drain current (ID(lin): The drain current when the transistor is biased in the linear region. NOTE Typical bias voltages for ID(lin) measu
31、rements are VDS(lin) = -0.1 V, VGS = -VDD and VBS = VBB. linear drain voltage (VDS(lin): The drain-to-source voltage for linear region measurements. NOTE Typically, VDS(lin) = -0.1 V. maximum operating junction temperature (TJ(max): The maximum junction temperature specification for a given technolo
32、gy. maximum linear transconductance (gm(max): The maximum slope of the ID-VGS curve in the linear region. NOTE 1 The gate voltage shall be varied in increments no greater than 20 mV from below the turn-on voltage to a value great enough to ensure that the maximum slope point has been reached. NOTE 2
33、 The slope shall be calculated using a three-point linear least-squares best-fit algorithm as defined in ASTM F617-86. NOTE 3 Typical bias voltages for gm(max) measurements are VDS = VDS(lin) and VBS = VBB. metal-oxide -semiconductor field-effect transistor (MOSFET): An insulated-gate field-effect t
34、ransistor in which the insulating layer between each gate electrode and the channel is oxide material; the gate is metal or another highly conductive material. NOTE See JESD77-B for further clarification of MOSFET terms. NBTI: Negative bias temperature instability. nominal bulk supply voltage (VBB):
35、 The nominal bulk voltage for a given technology. NOTE Typical VBB = 0. If VBB is not equal to zero, then VBB for a P-MOSFET is positive. nominal power supply voltage (VDD): The nominal supply voltage for a given technology. NOTE VDD is positive. n-well-to-source voltage (VNW,S): The n-well-to-sourc
36、e voltage. NOTE The n-well is the bulk of a P-MOSFET. JEDEC Standard No. 90 Page 4 3 Terms and definitions (contd) punch-through voltage (VPT): The reverse-bias drain voltage applied to the drain terminal that results in significant drain-to-source current even though the transistor is biased in its
37、 off state. NOTE 1 Punch-through is differentiated from junction breakdown in that the current path is from drain to source instead of from drain to substrate, as is the case of junction breakdown. NOTE 2 Typical dc bias voltages for VPT measurements on p-channel MOSFETs are VDS at ID = -1 A and VGS
38、 = VBS = VBB. saturation drain current (ID(sat): The drain current when the transistor is biased in the saturation region. NOTE Typical bias voltages for ID(sat) measurements are VDS = VGS = -VDD and VBS = VBB. stress temperature (Tstress): The temperature at which the DUT is stressed during NBTI st
39、ress. NOTE If only one temperature experiment is run, it is recommmended that the stress temperature be at least the maximum allowed during circuit operation or the burn-in temperature if burn-in is included. test mode: The bias condition at which a given device parameter shift is monitored during t
40、he NBTI stress. test temperature (Ttest): The temperature at which the DUT is tested during the test of the device parameters during the NBTI stress. time to target (ttar): The time it takes under specific conditions for the value of a particular parameter to change by a specified amount or to a spe
41、cified value. NOTE For most other parameters, a change of 10% from the unstressed value is often used. For theshold voltage, a 10-mV change is often used. These values have been arbitrarily chosen, and no relationship to circuit failure is implied. Other criteria (e.g., 5% change from the unstressed
42、 value) may be used for a given technology. 4 Technical requirements 4.1 Equipment requirements The measurement system must be capable of the simultaneous application of voltage and measurement of current at the gate, drain, and substrate contacts of the transistor. The system must be able to measur
43、e 100 pA with a resolution of 1 pA or better. The voltage overshoot during parametric measurements and stress must not exceed 1% of the applied voltage. If ID(leak) needs to be tracked as a device parameter during the stress, the measurement apparatus needs to be capable to measure less than ID(leak
44、) . JEDEC Standard No. 90 Page 5 4 Technical requirements (contd) 4.2 Test structure requirements A p-channel MOSFET fabricated on an n-type well should be used. The minimum allowed channel length and width (particularly for a Shallow Trench Isolation (STI) process) is recommended, but other channel
45、 lengths and widths can also be used. In addition MOSFETs with the minimum gate oxide thickness allowed by the technology must be evaluated. The gate, drain and source contacts of the transistor must be contacted; i.e., they shall not be floating. The n-well contact must be set during stress/test to
46、 the same bias conditions as in operation. To minimize parasitic voltage drops between the applied drain stress voltage and the device, the resistances from the probe pads to the device source, drain, and substrate should be minimized. 4.3 Measurement Requirements The device should be set up at the
47、wafer level on a probe station providing a stable platform via a vacuum chuck or as a packaged part in a test fixture. Chuck or fixture temperature shall be set at the stress temperature during stress and test. Once set, this temperature must be maintained to within +/- 2.0 C of this set point for t
48、he duration of the test. At the end of each NBTI stress interval, the stress is terminated and device parameters are measured. The stress time interval should be known to an accuracy of +/- 1% for stress time intervals over 1 second and 10% for stress intervals less than 1 second. 5 The NBTI stress
49、test procedures Figure 1 describes the NBTI stress test procedure. Initial tests are used to select a “good“ device (see 5.2) and to determine initial unstressed parameter values. If the device is determined to be “good,“ data is recorded and the stress cycle begins. During the stress cycle the device is biased using the selected stress bias and temperature conditions. The device parameter measurements are carried out at the stress temperature. Since changes in parameters typically exhibit a power law behavior the recommended stress intervals are at leas
