1、MIL-C-L332D 70 9777706 0370037 O W T - 59 -YS MIL-C-81332D (AS) 26 November 1981 SUPERSEDING 9 April 1981 MIL-C-81332C(AS) MILITARY SPECIFICATION COMPUTER SET , DIGITAL AN/ASQ-114 (V) This specification is approved for use by the Naval Air Systems Command, Department of the Navy, and is available fo
2、r use by all Departments and Agencies of the Department of Defense, 1. SCOPE 1.1 Scope - the functions of the digital data processor in an integrated airborne system. The equipment covered by this speciffcation shall perform 1.2 Classification - The Digital Computer Set, consisting of the items list
3、ed in 6.8, shall be classified in accordance with the following nomen- clature and characteristics (see 6.6) : a, Under the following conditions, the computer set nomenclature shall be the AN/ASQ-114 (V) : (1) The bootstrap memory shall be a 512 word core rope, (2) The number of input channels shall
4、 be 12 (see 3.5.3.1). (3) nondestructive readout (NDRO) memory (see 3.5.1.5.1.8). The memory unit shall have interconnection cables between the sense amplifier maintenance modules and the memory stack maintenance modules (see 3.2.3.1). The interconnection cables are exclusive of the wire wrapped mem
5、ory unit interconnection panel (see 3.5.2.8). b. Under the following conditions, the computer set nomenclature shall be the AN/ASQ-114 (V) 3 : (1) (2) The number of input channels shall be 16 (see 3.5.3.1). (3) The bootstrap memory shall be a 1024 word NDRO Read Only Memory (ROM) (see 3.5.1.5.1.8).
6、The memory unit shall have interconnection cables between the sense amplifier maintenance modules and the memory stack maintenance module (see 3.2.3.1). The interconnection cables are exclusive of the wire wrapped memory unit interconnection panel (see 3.5.2.8). Beneficial Comments (recommendations,
7、 additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Commanding Officer, Naval Air Engineering Center, Engineering Specifications and Standards Department (ESSD) Code 93, Lakehurst, New Jersey 08733, by using the self-addressed Standard
8、ization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter. FSC 7021 -: :* Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- - MIL-C-8133ZD ?O W 777406 0270038 2 MIL-C-81332D(AS) c. The computer set nomencl
9、ature shall be AN/ASQ-l14(V) 4; (1) (2) (3) The bootstrap memory shall be a 1024 word ROM (see 3.5.1.5.1.8). The number of input channels shall be 16 (see 3.5.3.1), The memory unit interconnections between the .sense amplifier maintenance modules and the memory stack maintenance module (see 3.2.3.1)
10、 shall be through the wire wrapped interconnection panel (see 3.5.2.8). 2. APPLICABLE DOCUMENTS 2.1 Issues of Documents, date of invitation for bids or request for proposal,.form a part of this specification to the extent specified herein, The following documents of the issue in effect on n, SPECIFI
11、CATIONS tlilitary MIL-E-54 O0 J MIL-T-5422E MITPI-6181 6 Oct 1967 MIL-C- 6781B MIL-M-77 93C MILE-17555F MITrT-18303B MIL-N-18307C MIL-C-81511A STANDARDS Federal FED-STD-595A Military MITPSTD-275B Change 1 - 24 June 1966 I Electronic Equipment, Aircraft, General Specification for Testing, Environment
12、al, Aircraft Electronic Interference, Control Requirements, Aircraft Equipment Control Panel; Aircraft Equipment, Rack or Console Mounted Meter, Time Totalizing Electronic and Electrical Equipment, and Associated Repair Parts, Pieparation for Delivery of Test Procedures: Preproduction, Acceptance fo
13、r Aircraft Electronic Equipment, format for Nomenclature and Nameplates for Aeronautical Electronics and Associated Equipment Connector, Electric, Circular, High Density, Quick Disconnect, Environment Resisting, General Specification for Colors Printed Wiring for Electronic Equipment 2 Provided by I
14、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-C-L332D 70 m 7777706 0170037 9 m MIL-S TD-415B MIL-STD-470 21 Mar 1966 MIL-S TD- 4 7 1 15 Feb 1966 MIL- S TD- 48 O 30 Oct 1968 MIL-STD-681B MIL-S TD- 7 04A Change 1 - 7 Feb 1968 MIL-S TD-7 5 6A MIL-STD-781B MIL-
15、STD-785 30 June 1965 MIL-STD-794A MIL-STD-1130 12 Nov 1965 HANDBOOK Military MIL-HDBKL217A PUBLICATIONS - Test Points and Test Facilities Design Standard for - Maintainability Program Requirements (for Systems and Equipments) - Maintainability Demonstrations - Configuration Control, Engineering Chan
16、ges, Deviations and Wa iv er s - Identification Coding and Application of Hook up and Lead Wir e - Electric Power, Aircraft, Characteristics and Utilization of - Reliability Prediction - Test Levels and Accept/Rej ect Criteria for Reliability of Non-Expandable Electronic Equipment Requirements for R
17、eliability Program (for systems and equipments) Parts and Equipment, Procedures for Packaging and Packing of - - - Connections, Electrical, Solderless Wrap - Reliability Stress and Failure Rate Data for Electronic Equipment Naval A however, programs used on the CP-823/U computer, shall be capable of
18、 being run on this computer, when the maximum memory utilized by the program is 32,768 words. *3.5.1.5.4 Instruction Repertoire Characteristics - The computer shall be capable of executing the Instruction specified in Table III, and the instruction interpretation shall be as set forth in Appendix A.
19、 3.5.1.5.4.1 Format I Instruction Word - The Format I instruction words are used to implement non-input/output instructions and have the format shown in Figure 1, Appendix A contains information on the instructions. Overlap Operation - The Central Processor shall contain the 3.5.1.5.4.2 Format I 1/0
20、 Instruc,tion Word - Format I input/output instruction words are used to implement input/output instructions and have the format shown in Figure 2, the instructions. Appendix A contains information on 3.5.1.5.4.3 Format II General instruction Word - The Format II general instruction words provide ad
21、ditional instructions in the computer by providing instruction variations with a basic function code (f) of 77. InstructSon interpretation is performed on the next lower six bits. Appendix A contains information on the instructions and the format is shown in Figure 3. 3.5.1.5.4.4 instruction words a
22、re used to provide additional instructions in the Format I1 Special Instruction Word - The Format 11 special computer by providing instruction variations with a basic function code (f) of 77, and has the format shown in Figure 4. instruction information. See Appendix A for specific 14 Provided by IH
23、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-C-BL332D 70 7777706 OL70051 5 MIL-C-81332D(AS) 17 16 15 3-24 J in 15Bit mode (Direct Mdrorring) 14-11 10 O y Page me. Absolute Pige Rep i s ter Der igartor 23 22 21 , 20 19 18 L designetor I , J derfgnrtor f = in
24、rtnction code (in octal) b = B index deripnator (in octal) I 290-s24 23122 21 #) 19 18 I7 16 15 1% 178 y in I5Bft mod6 (Direct Mdretribg 14-11 10 - O J Page Me Ahsolute Page Register Derignator % % 678 6% % 15 b = B index designator (in octal) f dotignator f = ekraml (in octal) Provided by IHSNot fo
25、r ResaleNo reproduction or networking permitted without license from IHS-,-,- MIL-C-11332D 70 W 779990b 01170052 7 23-18 17-15 448 648 638 - y in 15-Bit Direct AddressingMsde 14- 11 104 bo y in Page Mode AP designator f = 77 Repreeents a Format X netruction I Figure 3. Format II General Instruction
26、658 23 t-, 18 -b= B index desiqnator (in octal) 508 540 14- 11 174-015 10 O 8 - ( irect orpage aode A k designator k = O, k-1 kit k33 29 4- 24 I = 77 Sbprerontir 8 Format II htructioa Ngum 4. Fomt II Spedal Inetructim F B index designator (in octal) rnction Code I y operand I Format II Function Code
27、 f = 77 Rcpreeenti a Fornut II Intmth Figure 5. Format II Dfnct Addrerrng Instrucoa I 16 PROBLEM HARD COPY Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-a L .r C + L E P E C + a a ar 5 i U E + ). c I- U U 4 + c MIL-C-L332D 70 7777906 0370053 9 W n
28、. U 9 9 -4 9 9 c C c c r) 0 C O C O Is 17 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- e 099999999699999999669999 I I 1 I . 18 PROBLEM HARD COPY Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL
29、-C-Bli332D 70 = 7779706 0170055 2 - MIL-C-81332D(AS) t, io999 tttt d d69 I 4 cc c c 4444 9999 WP EEEE t q9t4tt4tt I C r( n 3 ? # O Y C . k O Y m C QI d o 9 U r) .) i5 O Y o 3 o E Y O C o O O O : 4 Y C O 4 Y Y 2 o C n 19 Provided by IHSNot for ResaleNo reproduction or networking permitted without lic
30、ense from IHS-,-,-3.5.1.5.4.5 direct addressing instructions provide additional instructions in the computer to direct address up to 131,072 words of memory. the function code 77 is used and the format is shown in Figure 5. Format II Direct Addressing Instruction Word - The Format II A variation of
31、3.5.1.5.5 Program Interrupts - Provisions shall be made for the interrup- tion of a running program by an event which may occur asynchronously with that program. An interrupt shall suspend the normal program sequence and cause the execution of the instruction located in a permanently assigned interr
32、upt entrance address. The interrupts and their priority of execution shall be as specified in paragraphs 3.5.1.5.5.1 through 3.5.1.5.5.6. 3.5.L.5.5.1 Power On (Start) - This signal, while not an interrupt, shall be initiated with the highest priority and takes precedence over all interrupts. 3,5.1.5
33、,5.2 Power Failure Interrupt - This interrupt shall be initiated when an out-of-tolerance input voltage transient is detected. failure interrupt shall.be the highest priority interrupt within the computer, and it shall interrupt all equal or lower priority interrupts and lock out the initiation of a
34、ll lower priority interrupts until released. The power 3,5.1.5.5.3 Program Fault Interrupt - This interrupt shall be initiated whenever an instruction with an illegal function code (f=OO, 7700 or 7777) is executed. priority interrupt; it shall interrupt all equal or lower priority interrupts and loc
35、k out the initiation of all lower priority interrupts until released. The program fault interrupt shall be the second highest 3.5.1.5.5.4 Memory Protect Interrupt - This interrupt shall be initiated whenever an instruction is executed that initiated a memory write cycle into a protected memory area.
36、 highest priority interrupt; it shall interrupt all equal or lower priority interrupts and lock out the initiation of all lower priority interrupts. The memory protect interrupt shall be the third 3.5.1.5.5.5 when the clock memory register (000161) is decremented to zero. The count down clock shall
37、be enabled, set to the desired time, or disabled, set to zeros, under program control. The Count Down Clock Interrupt shall be the fourth highest priority interrupt; it shall interrupt all equal or lower priority interrupts and lock out the initiation of all lower priority interrupts. Count Down Clo
38、ck Interrupt - This interrupt shall be initiated *3,5.1.5.5.6 follows: 1/0 Interrupts - The 1/0 Interrupts shall be subdivided as a. A monitor interrupt shall be initiated when an input, output, or external function buffer with monitor terminates at the end of the transfer and an external interrupt
39、word has been stored at the preassigned memory location for the channel. The computer will treat an external interrupt as a monitor interrupt however, the computer will use the proper monitor interrupt preassigned memory location for the channel. 20 Provided by IHSNot for ResaleNo reproduction or ne
40、tworking permitted without license from IHS-,-,-MIL-C-L332D 70 799990b 0370057 b MI L-C-81332D( AS ) b. An intercomputer time-out interrupt shall be initiated whenever the transmitting computer has not received acknowledgement of the trans- mitted command or data word between computers within a spec
41、ified the. The length of the time period used with the time-out may vary; therefore, a user may specify, when the order is placed, any time period value in n accordance with the formula t (time-out) = 1/A X 2 -second, where n may be any integer from O to 29, and A is the internal or external real ti
42、me clock frequency. c. An external interrupt shall be initiated when the computer has set the interrupt enable,theexternal device places the interrupt word on the data lines and sets the external interrupt request signal line. 1/0 interrupts shall take the fifth highest interrupt priority. 1/0 prior
43、ity shall be as defined in paragraph 3.5.3.1.2.10. interrupt shall lock-out the initiation of all other Il0 interrupts until released. Any 1/0 *3.51.6 Components - pluggable, printed circuit modules containing integrated circuit packages, and a minimum amount of discrete network elements (Type 1, Ty
44、pe 2, and Type 5 or Type 1, Type 2, Type 6 and Type 7 maintenance modules). 3.5.1.7 Absolute Page Address Registecs (APR) - Addressing for memory greaterzthan 32,768 words is accomplished by the use of Abcoltue Page Registers, in a translation table, to translate a 15-bit address into a l/-bit addre
45、ss for a maximum of 131,072 word memory. 2048 words. The Central processor Unit shall be comprised of The page size will be The amount of memory to be addressed at any one time is 32,768 words. Sixteen APRs will be used, each APR 7 bits long. Four bits of the 15-bit address (Y or P are used to speci
46、fy one of the 16 APRs, 6 bits of the APR plus the remaining 11 bits of the address word are concatenated to produce a l/-bit address (see Figure 6). The remaining 1 bit of the APR- will indicate if the memory locarion is in a memory-protect mode. 3.5.2 Memory Unit - The Memory Unit shall meet the fo
47、llowing requirements: 3.5.2.1 Function - overlapped mode. thirty-bit destructive readout (DRO) words or a multiple f 16K. provide the overlapped mode shall require a minimum of two units of 16K, thirty-bit DRO words each. 3.5.2.2 Form Factor - inches wide by 12.6 inches high by 14.4 inches long (han
48、dles and alignment pins excluded). The memory shall be capable of being operated in the Each overlapped sgment shall be a minimum of 16K, TO Each Memory Unit shall be enclosed in a case 5.5 “3.5.2.3 Weight - The weight of each Memory Unit shall not exceed 35.5 pounds. 3.5.2.4 word DRO core memory st
49、acks and the associated electronics. be expandable in 8,192 word increments. DRO Memory - Memory Units shall be composed of up to four 4,096 Memory shall 21 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- - NIL-C-BL332D 70 9499406 0370058 MI L-C-81332D( AS) I Y GIVEN ADDRE
