1、 TIA-644-A-2001 APPROVED: JANUARY 30, 2001 REAFFIRMED: DECEMBER 7, 2012 TIA-644-A (Revision of TIA-644) February 2001Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits NOTICE TIA Engineering Standards and Publications are designed to serve the public interest
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19、HESE CONTENTS WOULD NOT BE PUBLISHED BY TIA WITHOUT SUCH LIMITATIONS. ELECTRICAL CHARACTERISTICS OF LOW VOLTAGE DIFFERENTIAL SIGNALING(LVDS) INTERFACE CIRCUITS(From TIA/EIA Standard TIA/EIA-644 and Standards ProposalNo. 4584 formulated under the cognizance of TIASubcommittee TR-30.2 on Data Transmis
20、sion Interfaces and Protocols)Contents Page1 SCOPE . 12 DEFINITIONS, SYMBOLS AND ABBREVIATIONS . 22.1 Data signaling rate 22.2 DTE. 22.3 DCE 22.4 LVDS 22.5 Star (*) 23 APPLICABILITY. 33.1 General applicability. 33.2 Data signaling rate 34 ELECTRICAL CHARACTERISTICS. 54.1 Generator characteristics. 5
21、4.1.1 Full load test measurements. 64.1.2 Offset voltage and balance measurements 74.1.3 Short-circuit measurements. 84.1.4 Output signal waveform 84.1.5 Dynamic output signal balance 94.2 Load characteristics .104.2.1 Receiver input current - voltage measurements.114.2.2 Receiver input balance meas
22、urements 114.2.3 Terminating receiver input current - voltage measurements and inputimpedance measurements 124.2.4 Receiver input sensitivity measurements .144.2.5 Media termination.154.3 Interconnecting media electrical characteristics164.3.1 Cable media174.3.1.1 Maximum dc loop resistance (DCR):17
23、4.3.1.2 Characteristic impedance:.17TIA/EIA-644-Aii4.3.1.3 Additional parameters174.3.2 PC Board trace media .174.3.3 Other media.174.4 System parameters.174.4.1 Multiple receiver operation.174.4.2 Failsafe operation.194.4.3 Total load limit195 ENVIRONMENTAL CONSTRAINTS.206 CIRCUIT PROTECTION.217 OP
24、TIONAL GROUNDING ARRANGEMENTS.227.1 Signal common (ground)227.1.1 Configuration “A“.227.1.2 Configuration “B“.237.2 Shield ground - cable applications23A.1 INTERCONNECTING CABLE24A.1.1 Length.24A.1.2 Typical cable characteristics25A.1.2.1 Parallel interface cable .25A.1.2.1.1 Parallel cable, physica
25、l characteristics25A.1.2.1.2 Parallel cable, electrical characteristics 25A.1.2.2 Serial interface cable26A.1.2.2.1 Serial cable, physical characteristics.26A.1.2.2.2 Serial cable, electrical characteristics.26A.1.3 Cable termination26A.2 CABLE LENGTH VS. DATA SIGNALING RATE GUIDELINES.27B.1 COMPATI
26、BILITY WITH OTHER INTERFACE STANDARDS.28B.1.1 Compatibility with IEEE 1596.3.28B.1.2 Inter-operation with other interface standards28B.2 RELATED TIA/EIA STANDARDS29B.3 OTHER RELATED INTERFACE STANDARDS .29TIA/EIA-644-AiiiFOREWORD(This foreword is not part of this Standard)This Standard was formulate
27、d under the cognizance of TIA Subcommittee TR-30.2 onData Transmission Interfaces.This Standard was developed in response to a demand from the data communicationscommunity for a general-purpose high-speed interface standard for use in high throughputDTE-DCE interfaces.The voltage levels specified in
28、 this Standard were specified such that maximum flexibilitywould be provided, while providing a low power, high speed, differential interface.Generator output characteristics are independent of power supply, and may be designedfor standard +5 V, +3.3 V or even power supplies as low as +2.5 V. Integr
29、ated circuittechnology may be BiCMOS, CMOS, or GaAs technology. The low voltage (330 mV)swing limits power dissipation, while also reducing radiation of EMI signals. Differentialsignaling provides multiple benefits over single-ended signaling, notably common-moderejection, and magnetic canceling.Add
30、itional specifications for multidrop applications have been incorporated into TIA/EIA-644-A. A full load test measurement for the generator and a balance test of receiver inputcurrent have been added to this revision. A survey of devices conforming to TIA/EIA-644currently available are able to meet
31、the additional requirements of TIA/EIA-644-A.This Standard includes two Annexes, both are informative only. Annex A providesguidelines for application, addressing data signaling rate and cable length issues. Annex Bprovides comparison information with other interface standards, and related standards
32、.TIA/EIA-644-A11 SCOPEThis Standard specifies the electrical characteristics of low voltage differential signalinginterface circuits, normally implemented in integrated circuit technology, that may beemployed when specified for the interchange of binary signals between:Data Terminal Equipment (DTE)
33、and Data Circuit-Terminating Equipment (DCE),Data Terminal Equipment (DTE) and Data Terminal Equipment (DTE),or in any point-to-point, or multidrop interconnection of binary signals between equipment.The interface circuit includes a generator connected by a balanced interconnecting mediato a load co
34、nsisting of a termination impedance and a receiver(s). The interfaceconfiguration is a point-to-point or multidrop interface. The electrical characteristics of thecircuit are specified in terms of required voltage, and current values obtained from directmeasurements of the generator and receiver (lo
35、ad) components at the interface points.The logic function of the generator and the receiver is not defined by this Standard, as it isapplication dependent. The generators and receivers may be inverting, non-inverting, ormay include other digital blocks such as parallel-to-serial or serial-to-paralle
36、l converters toboost the data signaling rate on the interchange circuit as required by the application.Minimum performance requirements for the balanced interconnecting media are furnished.Guidance is given in Annex A, Section A.2 with respect to limitations on data signaling rateimposed by the para
37、meters of the cable length, attenuation, and crosstalk for individualinstallations for a typical cable media interface.It is intended that this Standard will be referenced by other standards that specify thecomplete interface (i.e., connector, pin assignments, function) for applications where theele
38、ctrical characteristics of a low voltage differential signaling interface circuit is required.This Standard does not specify other characteristics of the DTE-DCE interface (such assignal quality, protocol, maximum data signaling rate, bus structure, and/or timing)essential for proper operation acros
39、s the interface.When this Standard is referenced by other standards or specifications, it should be notedthat certain options are available. The preparer of those standards and specificationsmust determine and specify those optional features which are required for that application.TIA/EIA-644-A22 DE
40、FINITIONS, SYMBOLS AND ABBREVIATIONSFor the purposes of this Standard, the following definitions, symbols and abbreviationsapply:2.1 Data signaling rateData signaling rate - expressed in the units b/s (bits per second), is the significantparameter. It may be different from the equipments data transf
41、er rate, which employs thesame units. Data signaling rate is defined as 1/tui where tui is the minimum intervalbetween two significant instants.2.2 DTEData Terminal Equipment2.3 DCEData Circuit-Terminating Equipment2.4 LVDSLow Voltage Differential Signaling2.5 Star (*)Star (*) - represents the oppos
42、ite input condition for a parameter. For example, the symbolQ represents the receiver output state for one input condition, while Q* represents theoutput state for the opposite input state.TIA/EIA-644-A33 APPLICABILITY3.1 General applicabilityThe provisions of this Standard may be applied to the cir
43、cuits employed at the interfacebetween equipments where information being conveyed is in the form of binary signals.Typical points of applicability for this Standard are depicted in Figure 1.DTEDCEGR GRBBLegend:DTE = Data Terminal Equipment DCE = Data Circuit-termination EquipmentG = Generator R = R
44、eceiverB = Balanced interconnecting mediaFigure 1 - Application of LVDS interface circuitsThe LVDS interface is intended for use where any of the following conditions prevail:a. The data signaling rate is too great for effective unbalanced (single-ended)operation.b. The data signaling rate exceeds t
45、he capability of TIA/EIA-422, TIA/EIA-485, orTIA/EIA-612 balanced (differential) electrical interfaces.c. The balanced interconnecting media is exposed to extraneous noise sources thatmay cause an unwanted voltage up to 1 V measured differentially between thesignal conductor and circuit common at th
46、e load end of the cable with a 50 resistor substituted for the generator.d. It is necessary to minimize electromagnetic emissions and interference with othersignals.3.2 Data signaling rateThe LVDS interface circuit will normally be utilized on data and timing, or control circuits.Actual maximum data
47、 signaling rate is NOT defined by this Standard. The limit isTIA/EIA-644-A4determined by the generator transition time characteristics, the media characteristics, thedistance between the generator and the load, and the required signal quality.A theoretical maximum limit is calculated at 1.923 Gb/s,
48、and is derived from a calculationof signal transition time at the load assuming a loss-less balanced interconnecting media.The recommended signal transition time (tr or tf) at the load should not exceed 0.5 of theunit interval to preserve signal quality. This Standard specifies that the transition t
49、ime ofthe generator into a test load be 260 ps or slower. Therefore, with the fastest generatortransition time, and a loss-less balanced interconnecting media, and applying the 0.5restriction, yields a minimum unit interval of 520 ps or 1.923 Gb/s theoretical maximumdata signaling rate. Employing a parallel bus structure (4, 8, 16, 32, etc. - bus width) caneasily extend the obtainable equivalent bit rate into the multi-Gb/s range.A recommended maximum data signaling rate is derived from a calculation of signaltransition time at the load. For example, if a cable media is selected, a max
