1、 INTERNATIONALSTANDARD IEC61691-5First edition2004-10IEEE 1076.4Behavioural languages Part 5: VITAL ASIC (application specific integrated circuit) modeling specification Reference number IEC 61691-5(E):2004 IEEE Std. 1076.4(E):2000 Publication numbering As from 1 January 1997 all IEC publications ar
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8、s Part 5: VITAL ASIC (application specific integrated circuit) modeling specification INTERNATIONALSTANDARD IEC61691-5First edition2004-10IEEE 1076.4Commission Electrotechnique InternationaleInternational Electrotechnical Commission Copyright IEEE 2004 All rights reserved IEEE is a registered tradem
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14、be in conformity with an IEC Publication. 6) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC/IEEE 61691-5 has been
15、processed through IEC technical committee 93: Design automation. The text of this standard is based on the following documents: IEEE Std FDIS Report on voting 1076.4 (2000) 93/194/FDIS 93/199/RVD Full information on the voting for the approval of this standard can be found in the report on voting in
16、dicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives. The committee has decided that the contents of this publication will remain unchanged until 2005. 4 IEC 61691-5:2004(E)IEEE 1076.4-2000(E)Published by IEC under licence from IEEE. 2004 IEEE. All
17、rights reserved. IEC 61691 consists of the following parts, under the general title Behavioural languages: IEC/IEEE 61691-1-1, Part 1: VHDL language reference manual IEC 61691-2, Part 2: VHDL multilogic system for model interoperability IEC 61691-3-1, Part 3-1: Analog description in VHDL (under cons
18、ideration) IEC 61691-3-2, Part 3-2: Mathematical operation in VHDL IEC 61691-3-3, Part 3-3: Synthesis in VHDL IEC 61691-3-4, Part 3-4: Timing expressions in VHDL (under consideration) IEC 61691-3-5, Part 3-5: Library utilities in VHDL (under consideration) IEC/IEEE 61691-4, Part 4: Verilog hardware
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39、rved. IEEE Standard for VITAL ASIC (Application Specic Integrated Circuit) Modeling SpecicationSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyApproved 21 September 2000IEEE-SA Standards BoardAbstract:The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specication
40、 isdened in this standard. This modeling specication denes a methodology which promotes thedevelopment of highly accurate, efcient simulation models for ASIC (Application-Specic Integrat-ed Circuit) components in VHDL.Keywords:ASIC, computer, computer languages, constraints, delay calculation, HDL,
41、modeling,SDF, timing, Verilog, VHDL7IEC 61691-5:2004(E)IEEE 1076.4-2000(E)Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. Copyright 2001 IEEE. All rights reserved.The objectives of the VITAL (VHDL Initiative Towards ASIC Libraries) initiative can be summed up in onesentence
42、:Accelerate the development of sign-off quality ASIC macrocell simulation libraries written in VHDL byleveraging existing methodologies of model development.The VITAL ASIC modeling specification is a revision of the IEEE 1076.4-1995, IEEE Standard for VITALASIC Modeling Specification. Several new mo
43、deling enhancements have been added to the standard andseveral usability issues which have been raised with the 1995 standard have been addressed. The newenhancements and usability improvements addressed include: Standardized ASIC memory models Support of IEEE VHDL93 and SDF 1497 standards Multisour
44、ce interconnect timing simulation SKEW constraint timing checks Timing constraint checks feature enhancements Additional generics to control X generation and message reporting for glitches and timing con-straints. Negative constraint calculation enhancement for vector signals to support memory model
45、s Fast delay path disable Negative glitch preemptionThese new features will improve the functional, timing accuracy significantly and aid performance of gatelevel VHDL simulations.The major enhancement is the definition of a ASIC memory modeling standard. With the addition of memorymodel package VIT
46、AL_Memory, a standard is defined which allow memory models to be coded in VHDLmore efficiently. The standard VITAL memory model package provides a method to represent memories,procedures and functions to perform various operations and the definition of a modeling style that promotesconsistency, main
47、tainability and tool optimization. This standard does not define modeling behavior ofspecific memories. The scope of the memory model standard is currently restricted to ASIC memorymodeling requirement for static RAMs and ROMs. The VITAL memory modeling enhancements arespecified in Clause 10 through
48、 Clause 12. The VITAL standard memory package is found in Clause 13.The memory model standard is derived from contributed work from the LSI Logic VHDL behavioral modeland Mentor Graphics Memory Table Model (MTM) techniques. The generous support of VHDLInternational provided the needed funding to tak
49、e these two contributed works and convert them into thememory specification and package code by the IEEE 1076.4 TAG (Technical Action Group) with significantcontribution coming from leading EDA services company GDA Technologies. The technical direction of the working group as well as the day to day activities of issue analysis and draftingof proposed wordings for the specification are the responsibility of the IEEE 1076.4 TAG. This group consistsof Ekambaram Balaji, Prakash Bare, Nitin Chowdhary, Jos
