1、 The Institute of Electrical and Electronics Engineers, Inc.345 East 47th Street, New York, NY 10017-2394, USACopyright 1993 by the Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 1993. Printed in the United States of AmericaISBN 1-55937-299-0No part of this pub
2、lication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher.IEEE Std 1164-1993IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)SponsorDesign Automation Technical Committeeof theIEEE
3、 Computer SocietyApproved March 18, 1993IEEE Standards BoardAbstract: This standard is embodied in the Std_logic_1164 package declaration and the semanticsof the Std_logic_1164 body. An annex is provided to suggest ways in which one might use thispackage.Keywords: Std_logic_1164, VHDL model interope
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12、y, IEEE Standards Board445 Hoes LaneP.O. Box 1331Piscataway, NJ 08855-1331USAIEEE Standards documents are adopted by the Institute of Electrical and ElectronicsEngineers without regard to whether their adoption may involve patents on articles,materials, or processes. Such adoption does not assume an
13、y liability to any patentowner, nor does it assume any obligation whatever to parties adopting the standardsdocuments.iiiIntroductionThis introduction is not a part of IEEE Std 1164-1993, IEEE Standard Multivalue Logic System for VHDL ModelInteroperability (Std_logic_1164).This package provides a st
14、andard datatype system for the declaration of ports and signals used in modelingdigital components in VHDL. Use of this package with its dened logic values and operators is intended toprovide a mechanism for writing VHDL component models that have well-dened behavior when connectedto other models ad
15、hering to this standard. Development of the Std_logic_1164 package: The work of this committee is the culmination of efforts by several groups with the same goals working overa period of over three years. The EIA (Electronic Industries Association) and the VDEG (VHDL DesignExchange Group) have been
16、working on the problem of interoperable VHDL component models since thestandardization of VHDL by the IEEE in 1987. The work at the EIA has been guided by John Wilner, JackKinn, and Len Finegold in their efforts to produce a specication for procuring interoperable VHDL compo-nent models. The work at
17、 the VDEG was guided by Moe Shahdad, Ghulam Nurie, and its last chair, VictorBerman, who merged this group with the IEEE Model Standards Group in order to promote a unied stan-dard. The VDEG group has since disbanded. At present there is agreement by the IEEE P1164 and EIA 567groups on this standard
18、. Between 1989 and this date, many individuals made valuable contributions to the development of this stan-dard. At the time of approval of the standard, the members of the working group were: William Billowitch,ChairDavid Ackley Andrew Guyler Zainalabedin NavabiGordon Adshead William A. Hanna Sivar
19、am Nayudu Shishir Agarwal John Hillawi Wolfgang W. NebelDavid G. Agnew Robert Hillman Lawrence J. OConnellJames R. Armstrong Frederick Hinchliffe Jan PukiteDaniel S. Barclay John Hines Eric John Purslow Victor Berman Elchanan Herzog SrinivasRaghvendraThomas H. Borgstrom Andreas Hohl Paul RamondettaM
20、ark Brown Andy Huang Deborah L. RooneyWalter H. Buckhardt Gongwen Huang Jacques Rouillard Scott Calhoun Mitsuaki Ishikawa Ashraf M. SalemDavid M. Cantwell Takashi Kambe Larry F. SaundersSteven Carlson Stanley J. Krolikoski Paul ScheidtHarold W. Carter Stephen Kun Kenneth E. Scott Moon Jung Chung How
21、ard K. Lane Moe ShadadDavid Coelho Rick Lazansky Lee A. ShombertTedd Corman Jean Lebrun David W. SmithAllen Dewey Oz Levia Alec G. Stanculescu Michael Dukes Alfred Lowenstein Balsha R. StanisicLen Finegold Joseph F.P. Luhukay Jose A. TorresJacques P. Flandrois Don MacMillen Joseph G. TrontAlain Fonk
22、oua F.Eric Marschner Cary Ussery Geoffrey Frank William S. McKinney Radha VaidyanathanGary Gaugler Paul J. Menchini James H. VellengaAlfred S. Gilman Jean Mermet Ranganadha VemuriEmil Girczyc Gerald T. Michael Karen E. Watkins Rita Glover Gabe Moretti Ronald WaxmanBrent Gregory Wolfgang Mueller Fran
23、cis WiestBrian Grifn John WinklerLawrence T. Groves Alex Zamrescu ivThe following persons were on the balloting committee that approved this document for submission to theIEEE Standards Board:When the IEEE Standards Board approved this standard on March 18, 1993, it had the following member-ship: Ma
24、rco W. Migliaro,ChairDonald C. Loughry,Vice ChairAndrew G. Salem,SecretaryDennis Bodson Donald N. Heirman T. Don Michael*Paul L. Borrill Ben C. Johnson John L. RankineClyde Camp Walter J. Karplus Wallace S. ReadDonald C. Fleckenstein Ivor N. Knight Ronald H. ReimerJay Forster* Joseph Koepnger* Gary
25、S. RobinsonDavid F. Franklin Irving Kolodny Martin V. SchneiderRamiro Garcia D. N. Jim Logothetis Terrance R. WhittemoreThomas L. Hannan Lawrence V. McCall Donald W. Zipse*Member EmeritusAlso included are the following nonvoting IEEE Standards Board liaisons:Satish K. AggarwalJames BeallRichard B. E
26、ngelmanDavid E. SoffrinStanley WarshawAdam H. SickerIEEE Standards Project EditorDavid Ackley Andrew Guyler Zainalabedin NavabiGordon Adshead William A. Hanna Sivaram Nayudu Shishir Agarwal John Hillawi Wolfgang W. NebelDavid G. Agnew Robert Hillman Lawrence J. OConnellJames R. Armstrong Frederick H
27、inchliffe Jan PukiteDaniel S. Barclay John Hines Eric John Purslow Victor Berman Elchanan Herzog SrinivasRaghvendraThomas H. Borgstrom Andreas Hohl Paul RamondettaMark Brown Andy Huang Deborah L. RooneyWalter H. Buckhardt Gongwen Huang Jacques Rouillard Scott Calhoun Mitsuaki Ishikawa Ashraf M. Sale
28、mDavid M. Cantwell Takashi Kambe Larry F. SaundersSteven Carlson Stanley J. Krolikoski Paul ScheidtHarold W. Carter Stephen Kun Kenneth E. Scott Moon Jung Chung Howard K. Lane Moe ShadadDavid Coelho Rick Lazansky Lee A. ShombertTedd Corman Jean Lebrun David W. SmithAllen Dewey Oz Levia Alec G. Stanc
29、ulescu Michael Dukes Alfred Lowenstein Balsha R. StanisicLen Finegold Joseph F.P. Luhukay Jose A. TorresJacques P. Flandrois Don MacMillen Joseph G. TrontAlain Fonkoua F.Eric Marschner Cary Ussery Geoffrey Frank William S. McKinney Radha VaidyanathanGary Gaugler Paul J. Menchini James H. VellengaAlf
30、red S. Gilman Jean Mermet Ranganadha VemuriEmil Girczyc Gerald T. Michael Karen E. Watkins Rita Glover Gabe Moretti Ronald WaxmanBrent Gregory Wolfgang Mueller Francis WiestBrian Grifn John WinklerLawrence T. Groves Alex Zamrescu vContentsCLAUSE PAGE1. Overview 11.1 Scope 11.2 Conformance with this
31、standard 12. Std_logic_1164 package declaration . 23. Std_logic_1164 package body . 4Annex A Using the Std_logic_1164 Package . 15A.1 Value system 15A.2 Handling strengths . 15A.3 Use of the uninitialized value 15A.4 Behavioral modeling for U propagation. 16A.5 Us related to conditional expressions.
32、 16A.6 Structural modeling with logical tables . 16A.7 X-handling: assignment of Xs 16A.8 Modeling with dont cares 16A.9 Resolution function 17A.10 Using Std_ulogic vs. Std_logic. 171IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)1. Overview 1.1 ScopeThis stand
33、ard is embodied in the Std_logic_1164 package declaration and the semantics of theStd_logic_1164 package body along with this clause 1 documentation. The information annex A is a guideto users and is not part of this standard, but suggests ways in which one might use this package. 1.2 Conformance wi
34、th this standard The following conformance rules shall apply as they pertain to the use and implementation of this standard: a) No modications shall be made to the package declaration whatsoever. b) The Std_logic_1164 package body represents the formal semantics of the implementation of theStd_logic
35、_1164 package declaration. Implementers of this package body may choose to simplycompile the package body as it is; or they may choose to implement the package body in the mostefcient form available to the user. Users shall not implement a semantic that differs from the formalsemantic provided herei
36、n.IEEEStd 1164-1993 IEEE STANDARD MULTIVALUE LOGIC SYSTEM FOR22. Std_logic_1164 package declaration - - - Title : Std_logic_1164 multivalue logic system - Library : This package shall be compiled into a library - : symbolically named IEEE. - : - Developers: IEEE model standards group (par 1164) - Pu
37、rpose : This packages defines a standard for designers - : to use in describing the interconnection data types- : used in VHDL modeling.- :- Limitation: The logic system defined in this package may- : be insufficient for modeling switched transistors,- : since such a requirement is out of the scope
38、of this- : effort. Furthermore, mathematics, primitives,- : timing standards, etc. are considered orthogonal- : issues in relation to this package and are therefore- : beyond the scope of this effort.- : - Note : No declarations or definitions shall be included in,- : or excluded from, this package.
39、 The “package declaration“- : defines the types, subtypes, and declarations of- : Std_logic_1164. The Std_logic_1164 package body shall be- : considered the formal definition of the semantics of- : this package. Tool developers may choose to implement- : the package body in the most efficient manner
40、 available- : to them.- :- - modification history :- - version | mod. date:|- v4.200 | 01/02/92 |- -PACKAGE Std_logic_1164 IS - - logic state system (unresolved) - TYPE std_ulogic IS ( U, - UninitializedX, - Forcing Unknown0, - Forcing 01, - Forcing 1Z, - High ImpedanceW, - Weak UnknownL, - Weak 0H,
41、 - Weak 1- - Dont care);- unconstrained array of std_ulogic for use with the resolution function- TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE ) OF std_logic;- common subtypes-SUBTYPE X01 IS resolved std_ulogic RANGE X TO 1; - (X,0,1)SUBTYPE X01Z IS resolved std_ulogic RANGE X TO Z; - (X,0,1,Z)SU
42、BTYPE UX01 IS resolved std_ulogic RANGE U TO 1; - (U,X,0,1)SUBTYPE UX01Z IS resolved std_ulogic RANGE U TO Z; - (U,X,0,1,Z)- overloaded logical operators-FUNCTION “and“ ( l : std_ulogic; r : std_ulogic ) RETURN UX01;FUNCTION “nand“ ( l : std_ulogic; r : std_ulogic ) RETURN UX01;FUNCTION “or“ ( l : s
43、td_ulogic; r : std_ulogic ) RETURN UX01;FUNCTION “nor“ ( l : std_ulogic; r : std_ulogic ) RETURN UX01;IEEEVHDL MODEL INTEROPERABILITY (Std_logic_1164) Std 1164-19933FUNCTION “xor“ ( l : std_ulogic; r : std_ulogic ) RETURN UX01;- FUNCTION “xnor“ ( l : std_ulogic; r : std_ulogic ) RETURN UX01;FUNCTION
44、 “not“ ( l : std_ulogic ) RETURN UX01;- vectorized overloaded logical operators-FUNCTION “and“ ( l, r : std_logic_vector ) RETURN std_logic_vector;FUNCTION “and“ ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;FUNCTION “nand“ ( l, r : std_logic_vector ) RETURN std_logic_vector;FUNCTION “nand“
45、( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;FUNCTION “or“ ( l, r : std_logic_vector ) RETURN std_logic_vector;FUNCTION “or“ ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;FUNCTION “nor“ ( l, r : std_logic_vector ) RETURN std_logic_vector;FUNCTION “nor“ ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;FUNCTION “xor“ ( l, r : std_logic_vector ) RETURN std_logic_vector;FUNCTION “xor“ ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;- - Note : The declara
