1、 IEEE Standard for Memory Modeling in Core Test Language (CTL) Sponsored by the Test Technology Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USA IEEE Computer Society IEEE Std 1450.6.2-2014IEEE Std 1450.6.2-2014 IEEE Standard for Memory Modeling in Core Test Language (CTL) Sponsor
2、Test Technology Standards Committee of the IEEE Computer Society Approved 27 March 2014 IEEE-SA Standards Board Abstract: Reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits is required for system-on-chip (SoC) tests. This s
3、tandard defines language constructs sufficient to represent the context of a memory core and of the integration of that memory core into an SoC. This facilitates the development and reuse of test and repair mechanisms for memories. This standard also defines constructs that represent the test struct
4、ures internal to the memory core for reuse in the creation of the tests for the logic outside the memory core. Semantic rules are defined for the language to facilitate interoperability between different entities (the memory core provider, the system integrator, and the automation tool developer) in
5、volved in the creation of an SoC. The capabilities are an extension of IEEE Std 1450.6-2005. As a result of this extension, CTLs limitations of handling memories are addressed. Keywords: core test language (CTL), IEEE 1450.6.2, memory built-in self-test (memory BIST), memory modeling, memory repair,
6、 standard test interface language (STIL), system-on-chip (SoC) The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright 2014 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 13 June 2014. Printed in
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36、. vi Participants At the time this IEEE standard was completed, the Core Test Language Working Group had the following membership: Saman Adham, Chair Slimane Boutobza, Vice Chair Albert Au Tim Ayres Karen Darbinyan Prashant Dubey Geir Eide Rajat Mehrotra Vidya Neerkundar Gary Waggoner Past members i
37、nclude the following: Nicco Bhabu Jaynata Bhadar Dwayne Burek Rohit Kapur Srinivas Mandyam-Kumar Chandramouli Ramamurti The following members of the individual balloting committee voted on this standard. Balloters may have voted for approval, disapproval, or abstention. Saman Adham Juan Carreon Keit
38、h Chow Adam Cron Heiko Ehrenberg Randall Groves Peter Harrod Kazumi Hatayama Werner Hoelzl Rohit Kapur Anzou Ken-Ichi Adam Ley Benoit Nadeau-Dostie Jim OReilly Ulrich Pohl Paul Reuter Mike Ricchetti Thomas Starai Walter Struppler Srinivasa Vemuru Oren Yuen Daidi Zhong When the IEEE-SA Standards Boar
39、d approved this standard on 27 March 2014, it had the following membership: John Kulick, Chair Jon Walter Rosdahl, Vice Chair Richard H. Hulett, Past Chair Konstantinos Karachalios, Secretary Peter Balma Farooq Bari Ted Burse Clint Chaplin Stephen Dukes Jean-Philippe Faure Gary Hoffman Michael Janez
40、ic Jeffrey Katz Joseph L. Koepfinger* David J. Law Hung Ling Oleg Logvinov Ted Olsen Glenn Parsons Ron Petersen Adrian Stephens Peter Sutherland Yatin Trivedi Phil Winston Don Wright Yu Yuan *Member Emeritus Also included are the following nonvoting IEEE-SA Standards Board liaisons: Richard DeBlasio
41、, DOE Representative Michael Janezic, NIST Representative Julie Alessi IEEE-SA Content Publishing Kathryn Bennett IEEE-SA Technical Community Programs Copyright 2014 IEEE. All rights reserved. vii Introduction This introduction is not part of IEEE Std 1450.6.2-2014, IEEE Standard for Memory Modeling
42、 in Core Test Language (CTL). The core test language (CTL) defined in IEEE Std 1450.6-2005 is a modeling language created to enable design reuse for system-on-chip flows (or SoC flows). The base CTL standard does not address all memory-specific characteristics and structural information required to
43、create memory test and repair patterns. This extension of CTL adds support for modeling memories. Copyright 2014 IEEE. All rights reserved. viii Contents 1. Overview 1 1.1 General 1 1.2 Memory integration flow . 2 1.3 Scope . 2 1.4 Purpose 2 1.5 Limitations of this standard . 3 1.6 Structure of this
44、 standard . 3 2. Normative references 3 3. Definitions, acronyms, and abbreviations 4 3.1 Definitions . 4 3.2 Acronyms and abbreviations . 6 4. Extensions to IEEE Std 1450.6-2005 . 7 4.1 CTLMode - Internal blockextension of Data Type attributes 7 4.2 Addition to CTLMode Relation block 10 4.3 Port an
45、d Target for Purpose statementextensions to IEEE Std 1450.6-2005, Clause 16 11 4.4 Compatibility blockextension to IEEE Std 1450.6-2005, Clause 16 12 4.5 MemoryStructures blockextension to IEEE Std 1450.6-2005, Clause 6 16 4.6 FileReference blockextension to IEEE Std 1450.6-2005, Clause 8 17 5. Memo
46、ryRepair block .18 5.1 Syntax .18 5.2 MemoryRepair block syntax description 20 5.3 MemoryRepair Examples .22 6. MemoryPhysicalOrganization block .26 6.1 Syntax .26 6.2 MemoryPhysicalOrganization block syntax descriptions .27 6.3 MemoryPhysicalOrganization examples 29 7. Memory CTL Orientation and Ca
47、pabilities Tutorial .34 7.1 Example of 3-port (2R/1W) memory with repair .34 7.2 Example of Memory with Pipelining and Bit-Line Twisting .45 7.3 Example of Memory with Bank Addressing 49 7.4 Example of Memory with Error Correction Code 54 7.5 Example of memory with embedded comparators .58 Copyright
48、 2014 IEEE. All rights reserved. 1 IEEE Standard for Memory Modeling in Core Test Language (CTL) IMPORTANT NOTICE: IEEE Standards documents are not intended to ensure safety, security, health, or environmental protection, or ensure against interference with or from other devices or networks. Impleme
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