1、INTERNATIONAL STANDARD ISO/IEC 10861 ANSI/IEEE Std 1296 First edition 1994-04-27 Information technology- Microprocessor systems- High-performance synchronous 32-bit bus:. MULTIBUS II Technologies de Yin formation - Systtimes ti microprocesseurs - Bus 32 bits synchrone g haute performance: MUL TIBUS
2、II Reference number ISO/IEC 10861 : 1994(E) ANSI/IEEE Std 1296, 1994 Edition Abstract: The operation, functions, and attributes of a parallel system bus (PSB), called MULTI- BUS II, are defined. A high-performance backplane bus intended for use in multiple processor sys- tems, the PSB incorporates s
3、ynchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective, high-performance VLSI for the bus interface. Memory, I/O, message, and geographic
4、address spaces are defined. Error detection and retry are provided for messages. The message-passing design allows a VLSI implementation, so that virtually all mod- ules on the bus will utilize the bus at its highest performance-32 to 40 Mbyte/s. An overview of PSB, signal descriptions, the PSB prot
5、ocol, electrical characteristics, and mechanical specifications are covered. Keywords: high-performance synchronous 32-bit bus, MULTIBUS II, system bus architectures The Institute of Electrical and Electronics Engineers, Inc. 345 East 47th Street, New York, NY 10017-2394, USA Copyright 0 1994 by the
6、 Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 1994. Printed in the United States of America. ISBN l-55937-368-7 No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written pemV.ssion of
7、 the publisher. April 27, 1994 SH16766 lSO/lEC 10861 : 1994 ANSI/IEEE Std 1296,1994 Edition Information technology- Microprocessor systems- High-performance synchronous 32-bit bus: MULTIBUS II Sponsor Technical Committee on Microprocessors and Microcomputers of the IEEE Computer Society -Sib- EJ m A
8、dopted as an International Standard by the a!?/ International Organization for Standardization and by the International Electrotechnical Commission Published by The Institute of Electrical and Electronics Engineers, Inc. - American National Standard Foreword IS0 (the International Organization for S
9、tandardization) and IEC (the International Electrotechnical Commission) form the specialized system for worldwide standard- ization. National bodies that are members of IS0 or IEC participate in the develop- ment of International Standards through technical committees established by the respective o
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11、ology, IS0 and IEC have established a joint technical committee, ISO/IEC JTC 1. Draft International Standards adopted by the joint tech- nical committee are circulated to national bodies for voting. Publication as an Inter- national Standard requires approval by at least 75% of the national bodies c
12、asting a vote. In 1990, ANSI/IEEE Std 1296-1987 was adopted by ISO/IEC JTC 1, as draft Interna- tional Standard ISO/IEC/DIS 10861. This draft was subsequently approved by ISOI IEC JTC 1 in the form of this edition, which is published as International Standard ISO/IEC 10861 : 1994. International Orga
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23、troduction (This introduction is not a normative part of ISO/IEC 10861 : 1994 ANSVIEEE Std 1296, 1994 Edition, but is included for information only.) In the last decade, the avalanche of new microcomputer technology, especially VLSI, threatened to obsolete products almost before they went into produ
24、ction. To buffer users from this onrush of technology, Intel helped develop standard interfaces. One of the most notable was the MULTIBUS I system bus, which was used as the basis for a standard by the IEEE in 1983 as IEEE Std 796-1983 (after going through a 5-year review and revision process). In t
25、he early 198Os, Intel recognized that the trends toward multiprocessing and more sophisticated micro- computer-based systems called for an advanced 32-bit system bus architecture. Intel called this new bus MULTIBUS II. In continuing to pioneer the open systems technology, which included multiprocess
26、ing, four critical requirements were observed: technical credibility, processor independence, standardization, and openness to all levels of integration. Early in the development of the new bus, Intel established a “MULTI- BUS II Development Consortium.” The consortium gave the new bus a technical c
27、redibility that few buses, especially those defined only among board vendors, can match. The companies in the consortium also repre- sented all microprocessor families; included in the group were 68020, 32032, 80386, and 28000 board and system users, thus ensuring that the bus is easily adaptable to
28、 virtually any manufacturers processor. The primary benefits being sought in the creation of this new bus were high-performance multiprocessing, high system reliability, ease-of-use by system designers, and improved cost/performance. Specific bus features were developed in response to these objectiv
29、es. The 32 Mbyte/s message passing of the bus provides a bus that acts like a very high-speed network connection for multiple processors (or processor equivalents). There is a recognition that the bus is no longer to interconnect a CPU with its memory and I/O; instead the bus is to interconnect whol
30、e stand-alone processors with each other and with intelligent “sub- systems-on-a-board.” System reliability is enhanced by the features of bus parity, synchronous operation, negative acknowledge, transfer retries, geographic addressing, and advanced backplane design. Ease-of-use by system designers
31、is implemented primarily through the geographic addressing, which provides for dynamic system configura- tion. The bus encourages the use of software programmable configuration options (and discourages any use of mechanical jumpers). The standardization of the high-level message-passing protocol als
32、o gives the system designer an easy-to-use capability for interprocessor communication. The cost/performance objective of the bus is delivered through its specification of a realizable 32 to 40 Mbyte/s bus bandwidth. Virtually all boards designed to the bus can achieve this bus utilization factor du
33、e to the high-level protocol called out in the specification, and thus the availability of standard, high- performance and cost-effective VLSI components to actually implement this level of performance. For example, this specification and the VLSI make it possible for eight concurrent 4 megabyte/sec
34、ond transfers to take place on the bus. This, or other combinations of transfers that add up to 32 Mbyte/s, demonstrate the real cost/performance advantages of the bus for multiprocessor applications. In 1983 MULTIBUS II was introduced to the IEEE standards process as a part of the considerations fo
35、r the P896 (Future Bus) working group activities. In the 1984/1985 time frame the MSC (Microcomputer Stan- dards Committee, of the TCMM) formed an independent study group for MULTIBUS II. During this time the many active participants of the group proceeded to thoroughly review and make changes to th
36、e proposed draft. In early 1986 the group was assigned a formal project number P1296. During the remainder of 1986, the draft was passed by the Working Group and the MSC after thorough review, discussion, and changes. In 1987, the draft was presented for Sponsor ballot and, after passing, presented
37、to the June 1987 meeting of the IEEE Standards Board. iv The IEEE Standards Board calls attention to the fact that there are patents claimed and/or pending on many aspects of this bus by Intel Corporation. IEEE takes no position with respect to patent validity. Intel Corpo- ration has assured the IE
38、EE that it is willing to grant a license for these patents on reasonable and nondis- criminatory terms to anyone wishing to obtain such a license. The general terms of the license are a one-time administration fee of $100 for a nonexclusive perpetual license. Intel Corporations undertakings in this
39、respect are on file obtained from the legal department of Intel Corporation whose address is Intel Corpora- tion, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124. There were many contributors to the standards review process, but the following members deserve special mention for their active partic
40、ipation: Task Force Coordinators: Jack Blevins Maurice Hubert Hubert Kirrmann Jim Nebus Secretary of Working Group: Steve Cooper Original Study Group Chairman: Paul Borrill Original Draft Editor: Scott Tetrick The P1296 Working Group that prepared this standard had the following membership: Richard
41、W. Boberg, Chair Web Augustine Gene Freehauf Jack Blevins Maurice Hubert Paul Borrill Hubert Kirrmann Steve Cooper Klaus Mueller Tom Crawford Jim Nebus Don Nickel Ken Smith Michael Thompson Scott Tetrick Eike Waltz Janusz Zalewski The following members of the Technical Committee on Microprocessors a
42、nd Microcomputers were on the balloting body: Andrew Allison Peter J. Ashenden Matt Biewer John Black Jack Blevins Richard Boberg Paul Borrill Bradley Brown Clyde Camp John D. Charlton Steve Cooper Randy Davis J. Robert Davis Shirish P Deodhar Jim Dunlay Wayne Fischer Jim Flournoy Gordon Force Marti
43、n Freeman David Gustavson Tom Harkaway Dave Hawley David James Laurel Kaleda Richard Karpinski Hubert Kirrman Doug Kraft Tom Kurihara Glen Langdon Gerrv Laws Tom-Leonard Rollie Linser Gary Lyons James Nebus Gary Nelson Deene Ogden Tom Pittman Shlomo Pri-Tal P. Reghunathan Richard Rawson Bill Shields
44、 Michael Smolin Robert Stewart Subramanganesan Michael Teener Scott Tetrick Eike Waltz Carl Warren George White Fritz Whittington Tom Wicklund Andrew Wilson Anthony Winter V When the IEEE Standards Board approved this standard on June 11, 1987, it had the following membership: Donald C. Fleckenstein
45、, Chair Marco W. Migliaro, Vice Chair Andrew G. Salem, Secretary James H. Beall Dennis Bodson Marshall L. Cain James M. Daly Stephen R. Dillon Eugene R Fogarty Jay Forster Kenneth D. Hendrix Irvin N. Howell *Member Emeritus Leslie R. Kerr Jack Kinn Irving Kolodny Joseph L. Koepfinger* Edward Lohse J
46、ohn May Lawrence V. McCall L. Bruce McClung Donald T. Michael* L. John Rankine John R Riganati Gary S. Robinson Frank L. Rose Robert E. Rountree Sava I. Sherr* William R. Tackaberry William B. Wilkens Helen M. Wood IEEE Std 1296-1987 was approved by the American National Standards Institute on Febru
47、ary 8, 1987 and was reaffirmed by IEEE on March 17,1994. Contents CLAUSE PAGE 1. General overview to the IEEE 1296 Standard . 1 1.1 Scope 1 1.2 Normative references . 1 2. Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Guide to notation 7 3.1 General . 7 3.2 Signal notation . 7 3.3 Figure notation . 7 3.4 Notation in state-flow diagrams . 8 3.5 Notation for multiple bit data representati
49、on . 9 4. PSB overview . 10 4.1 General . 10 4.2 Address/data path and system control signals . 11 4.3 Message-passing facility 11 4.4 Interconnect facility . 11 4.5 Synchronous operation of the PSB 11 4.6 Bus operations on the PSB . 11 4.7 Central services module . 15 5. Signal descriptions . 16 5.1 General . 16 5.2 Signal groups . 16 6. PSB protocol 25 6.1 General . 25 6.2 Arbitration operation 25 6.3 Transfer operation 36 6.4 Exception operation . 54 6.5 Central control functions 58 6.6 State-flow diagrams . 64 7. Electrical characteristics 76 7.1 General . 76 7.2 AC timing specific
