1、 IEEE Standard for Static Component Interconnection Test Protocol and Architecture Sponsored by the Test Technology Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USA 20 June 2011 IEEE Computer Society IEEE Std 1581TM-2011IEEE Std 1581- 2011 IEEE Standard for Static Component Interco
2、nnection Test Protocol and Architecture Sponsor Test Technology Standards Committee of the IEEE Computer Society Approved 31 March 2011 IEEE-SA Standards Board Approved 27 March 2012 American National Standards Institute Abstract: IEEE Std 1581 defines a low-cost method for testing the interconnecti
3、on of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The s
4、tandard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry. Keywords: board test, connectivity test, IEEE 1581, integrated circuit, interconnect test, interconnection test, memory device, test log
5、ic, test mode, transparent test mode The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright 2011 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 20 June 2011. Printed in the United States of Amer
6、ica. IEEE is a registered trademark in the U.S. Patent +1 978 750 8400. Permission to photocopy portions of any individual standard for educational classroom use can also be obtained through the Copyright Clearance Center. iv Copyright 2011 IEEE. All rights reserved. Introduction This introduction i
7、s not part of IEEE Std 1581-2011, IEEE Standard for Static Component Interconnection Test Protocol and Architecture. In 1999, an idea was presented, at the International Test Conference (ITC), on testing the interconnections between certain complex memory devices that do not comply with IEEE Std 114
8、9.1 and other IEEE 1149.1 devices on a printed circuit board (PCB). The process of testing for interconnections is also referred to as interconnect testing and connectivity testing. The complex memories at which this technique is directed are those that cannot be conveniently tested using static tes
9、t techniques, such as boundary scan, because they involve high frequencies. Another reason is that those devices often contain a state machine that can be exercised only using data and address lines that are yet to be tested. The idea presented was a test method comprising a combinational function d
10、esigned into the memory. The combinational function replaced the memory function when the test mode was activated and did not otherwise interfere with memory operation of the memory. Thus, the complexity of the memory may be bypassed during test by the combinational function. The idea was described
11、in two papers. One paper described the theoretical background of the combinational function in relation to detection and diagnosis of defects (Biewenga et al. B1).aThe other paper described a practical approach: an implementation in synchronous dynamic random access memory (SDRAM) (de Jong et al. B2
12、). The novel idea attracted much attention from the test community. A fringe meeting at ITC was held and resulted in a plan to have this idea captured within a test standard. Since implementation would be within the silicon of memory devices, standardization was planned to start within JEDEC Solid S
13、tate Technology Association (JEDEC). It was later decided to first develop an IEEE standard, as this approach would lead to a more extensive and unambiguous description of the implementation. The continued need for JEDEC involvement was, however, clearly recognized. In 2000, first attempts were made
14、 to form a study group of people enthusiastic about this novel test concept. This group was the precursor of the IEEE working group. At the beginning of 2001, the P1581 Working Group was officially formed after having had two preliminary telephone conferences. Shortly after formation of the working
15、group, one member found an alternative to the method first introduced in 1999. This method, a simple extension of traditional connectivity tests such as NAND trees, etc., was brought to the attention of the working group in 2001. In addition, the original proposal for standardization was extended wi
16、th a number of test mode entry/exit methods as well as a set of general rules for test logic implementations. This standard is the result of the work performed to date by the P1581 Working Group. Notice to users Laws and regulations Users of these documents should consult all applicable laws and reg
17、ulations. Compliance with the provisions of this standard does not imply compliance to any applicable regulatory requirements. Implementers of the standard are responsible for observing or referring to the applicable regulatory requirements. IEEE does not, by the publication of its standards, intend
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22、en amended through the issuance of amendments, corrigenda, or errata, visit the IEEE Standards Association web site at http:/ieeexplore.ieee.org/xpl/standards.jsp, or contact the IEEE at the address listed previously. For more information about the IEEE Standards Association or the IEEE standards de
23、velopment process, visit the IEEE-SA web site at http:/standards.ieee.org. Errata Errata, if any, for this and all other standards can be accessed at the following URL: http:/standards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errata periodically. In
24、terpretations Current interpretations can be accessed at the following URL: http:/standards.ieee.org/reading/ieee/interp/ index.html. Patents Attention is called to the possibility that implementation of this standard may require use of subject matter covered by patent rights. By publication of this
25、 standard, no position is taken with respect to the existence or validity of any patent rights in connection therewith. The IEEE is not responsible for identifying Essential Patent Claims for which a license may be required, for conducting inquiries into the legal validity or scope of Patents Claims
26、 or determining whether any licensing terms or conditions provided in connection with submission of a Letter of Assurance, if any, or in any licensing agreements are reasonable or nondiscriminatory. Users of this standard are expressly advised that determination of the validity of any patent rights,
27、 and the risk of infringement of such rights, is entirely their own responsibility. Further information may be obtained from the IEEE Standards Association. vi Copyright 2011 IEEE. All rights reserved. Participants At the time this standard was submitted to the IEEE-SA Standards Board for approval,
28、the Static Component Interconnection Test Protocol and Architecture Working Group had the following membership: Heiko Ehrenberg, Chair Bob Russell, Vice Chair Adam Ley, Secretary Frans de Jong, Chair Emeritus Leon van de Logt, Editor Emeritus Steve Butkovich Jeff Halnon Joseph Kadaras Shuichi Kameya
29、ma Mike Laisne Kenneth P. Parker Rob Raaijmakers Bambang Suparjo Bradford van Treuren In the development of this standard, the working group was supported by many other individuals from many other organizations. The working group wishes to acknowledge the following people: Henrik Andersson Dave Bonn
30、ett Ben Bennetts Ian Burgess C. J. Clark Luis Cordova Adam Cron Ray Dellecker Ted Eaton Peter van den Eijnden Bill Eklow David Ford Bill Hovis James Huang Dennis Lia Patrick McHugh Gordon Robinson Pralhadrao Vasantbhatt Shantagiri Donald Smith Bernard Sutton The following members of the individual b
31、alloting committee voted on this standard. Balloters may have voted for approval, disapproval, or abstention. Keith Chow Frans G. De Jong Thomas Dineen Heiko Ehrenberg Timothy Ehrler Ron Greenthaler Randall Groves Jeff Halnon P. Harrod Werner Hoelzl Robert Holibaugh Paul Lambert Adam Ley Edward McCa
32、ll Ian McIntosh Jeffrey Moore Michael S. Newman Kenneth P. Parker Ulrich Pohl Mike Ricchetti Gordon Robinson Robert Robinson Bartien Sayogo Gil Shultz Walter Struppler Bambang Suparjo Srinivasa Vemuru Oren Yuen When the IEEE-SA Standards Board approved this standard on 31 March 2011, it had the foll
33、owing membership: Richard H. Hulett, Chair John Kulick, Vice Chair Robert M. Grow, Past Chair Judith Gorman, Secretary Masayuki Ariyoshi William Bartley Ted Burse Clint Chaplin Wael Diab Jean-Philippe Faure Alexander Gelman Paul Houz Jim Hughes Joseph Koepfinger* David J. Law Thomas Lee Hung Ling Ol
34、eg Logvinov Ted Olsen Gary Robinson Jon Walter Rosdahl Sam Sciacca Mike Seavey Curtis Siller Phil Winston Howard Wolfman Don Wright *Member Emeritus vii Copyright 2011 IEEE. All rights reserved. Also included are the following nonvoting IEEE-SA Standards Board liaisons: Satish Aggarwal, NRC Represen
35、tative Richard DeBlasio, DOE Representative Michael Janezic, NIST Representative Don Messina IEEE Standards Program Manager, Document Development Mike Kipness IEEE Standards Program Manager, Technical Program Development viii Copyright 2011 IEEE. All rights reserved. Contents 1. Overview 1 1.1 Scope
36、 . 1 1.2 Purpose 1 1.3 Organization of the standard 2 1.4 Context 2 1.5 IEEE 1581 defect model, detection, and diagnosis 4 1.6 Objectives 7 2. Normative references 7 3. Definitions, acronyms, and abbreviations 7 3.1 Definitions . 7 3.2 Acronyms and abbreviations 10 4. Test architecture 11 4.1 Overvi
37、ew 11 4.2 Combinational test logic architecture .13 4.3 Test mode architecture 13 5. Classification of device pins 14 5.1 Specification .14 5.2 Description .15 6. Test mode behavior .16 6.1 Specification .16 6.2 Description .16 7. Test mode control 20 7.1 Specification .20 7.2 Description .20 7.3 Te
38、st pin (TPN) 20 7.4 Transparent test mode (TTM) .22 7.5 Test pattern partitioning (TPP) .33 8. Test logic .42 8.1 Specification .43 8.2 Example implementation 1: XOR test logic .44 8.3 Example implementation 2: IAX test logic 45 8.4 Example implementation 3: XOR-2 test logic 47 9. Conformance and do
39、cumentation 49 9.1 Conformance 49 9.2 Documentation49 Annex A (informative) Bibliography 51 1 Copyright 2011 IEEE. All rights reserved. IEEE Standard for Static Component Interconnection Test Protocol and Architecture IMPORTANT NOTICE: This standard is not intended to ensure safety, security, health
40、, or environmental protection. Implementers of the standard are responsible for determining appropriate safety, security, environmental, and health practices or regulatory requirements. This IEEE document is made available for use subject to important notices and legal disclaimers. These notices and
41、 disclaimers appear in all publications containing this document and may be found under the heading “Important Notice” or “Important Notices and Disclaimers Concerning IEEE Documents.” They can also be obtained on request from IEEE or viewed at http:/standards.ieee.org/IPR/disclaimers.html. 1. Overv
42、iew 1.1 Scope This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1is not feasible. This standard describes the implementation
43、 rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry. 1.2 Purpose There is currently no defined, independen
44、t standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete making the test technology less usef
45、ul for others. This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting
46、 this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-l
47、evel connectivity faults on such devices. 1Information on normative references can be found in Clause 2. IEEE Std 1581-2011 IEEE Standard for Static Component Interconnection Test Protocol and Architecture 2 Copyright 2011 IEEE. All rights reserved. 1.3 Organization of the standard This standard is
48、divided into the following clauses: Clause 1 provides an overview and context for this standard. Clause 2 provides references necessary to understand this standard. Clause 3 describes the terms, definitions, and acronyms used in this standard. Clause 4 describes the test technology as applied for th
49、is standard and provides the motivation for using this standard. Clause 5 describes the classification of pins for an IEEE 1581 device. Clause 6 describes the behavior of an IEEE 1581 device while it is in test mode (versus functional mode). Clause 7 describes the test mode control protocol. It defines methods for test mode control of the device. Clause 8 describes the test architecture and test circuitry. This clause includes the specification of combinational logic functions for the test circuitry and provides examples of implementation an
