1、American National StandardDeveloped byfor Information Technology PCI Express Queuing Interface (PQI)INCITS 490-2014INCITS 490-2014INCITS 490-2014American National Standardfor Information Technology PCI ExpressQueuing Interface (PQI)SecretariatInformation Technology Industry CouncilApproved October 2
2、0, 2014American National Standards Institute, Inc.AbstractThis standard defines a circular queue interface for transferring information between a PQI host and a PQI device over the PCI Express architecture, and defines a scatter gather list (SGL) format that is used to describe data buffers.Approval
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14、 in the use ofthis standard.iContentsPageForeword . xIntroduction xv1 Scope . 12 Normative references . 22.1 Normative references overview 22.2 References under development . 22.3 Other references 23 Definitions, symbols, abbreviations, and conventions . 33.1 Definitions . 33.2 Symbols and abbreviat
15、ions 83.3 Keywords 83.4 Editorial conventions 93.5 Numeric and character conventions . 103.5.1 Numeric conventions 103.5.2 Units of measure . 113.5.3 Byte encoded character strings conventions 113.6 State machine conventions 123.6.1 State machine conventions overview 123.6.2 Transitions 133.6.3 Mess
16、ages, requests, indications, confirmations, responses, and event notifications . 133.6.4 State machine counters, timers, and variables . 133.6.5 State machine arguments . 133.7 Bit and byte ordering 143.8 Notation for procedure calls . 163.9 Notation for UML figures 163.9.1 Introduction . 163.9.2 Cl
17、ass notation . 183.9.3 Class association relationships notation . 193.9.4 Class aggregation relationships notation 203.9.5 Class generalization relationships notation . 213.9.6 Class dependency relationships notation . 223.9.7 Object notation 224 General concepts . 234.1 ASCII data field requirement
18、s 235 Model . 245.1 General overview . 245.2 PQI classes 265.2.1 PQI domain class 265.2.2 PQI host classes . 265.2.2.1 PQI host classes overview 265.2.2.2 PQI Host class . 285.2.2.3 PQI Host Management Application Client class 285.2.2.4 PQI Host Administrator OQ Information class . 285.2.2.5 PQI Hos
19、t Administrator IQ Information class . 285.2.2.6 PQI Host Operational Application Client Interface class . 285.2.2.7 PQI Host Operational OQ Information class . 295.2.2.8 PQI Host Operational IQ Information class . 295.2.3 PQI device classes . 305.2.3.1 PQI device classes overview . 305.2.3.2 PQI De
20、vice class . 33ii5.2.3.3 PD State Machine class 335.2.3.4 PQI Device Management Device Server class . 335.2.3.5 PQI Device Operational Device Server Interface class .335.2.3.6 Administrator OQ CI class . 335.2.3.7 Administrator IQ PI class . 335.2.3.8 Operational OQ CI class . 335.2.3.9 Operational
21、IQ PI class . 345.2.3.10 PQI Device Administrator OQ Information class . 345.2.3.11 PQI Device Operational OQ Information class 345.2.3.12 PQI Device Administrator IQ Information class . 345.2.3.13 PQI Device Operational IQ Information class 355.2.4 PQI service delivery subsystem classes . 355.2.4.1
22、 PQI service delivery subsystem classes overview 355.2.4.2 PQI Service Delivery Subsystem class . 365.2.4.3 PCI Express Fabric class 365.2.4.4 PQI Queue Structure class 365.2.5 Circular queue classes 375.2.5.1 Circular queue classes overview . 375.2.5.2 Circular Queue class . 385.2.5.2.1 Circular Qu
23、eue class overview 385.2.5.2.2 Element Array Address attribute 385.2.5.2.3 PI Address attribute . 385.2.5.2.4 CI Address attribute . 385.2.5.3 Element Array class 385.2.5.3.1 Element Array class overview 385.2.5.3.2 Number Of Elements attribute . 385.2.5.3.3 Element Length attribute 395.2.5.4 Elemen
24、t class 395.2.5.5 PI class 395.2.5.5.1 PI class overview . 395.2.5.5.2 Index attribute 395.2.5.6 CI class . 395.2.5.6.1 CI class overview . 395.2.5.6.2 Index attribute 395.2.5.7 IQ class . 395.2.5.7.1 IQ functional overview . 395.2.5.7.2 Example of IQ object locations that are not separated 415.2.5.
25、7.3 Example of IQ object locations that are separated 425.2.5.8 Administrator IQ class . 435.2.5.8.1 Administrator IQ class overview 435.2.5.8.2 Element Array Address attribute 435.2.5.8.3 Element Length attribute 435.2.5.8.4 Number Of Elements attribute . 435.2.5.8.5 PI Address attribute . 435.2.5.
26、8.6 CI Address attribute . 435.2.5.9 Operational IQ class 435.2.5.9.1 Operational IQ class overview . 435.2.5.9.2 IQ ID attribute 435.2.5.9.3 Element Array Address attribute 445.2.5.9.4 Element Length attribute 445.2.5.9.5 Number Of Elements attribute . 445.2.5.9.6 PI Address attribute . 445.2.5.9.7
27、 CI Address attribute . 445.2.5.9.8 Spanning Allowed attribute 445.2.5.9.9 Queue Protocol attribute 455.2.5.10 OQ class . 455.2.5.10.1 OQ functional overview 45iii5.2.5.10.2 Example of OQ object locations that are not separated 465.2.5.10.3 Example of OQ object locations that are separated 475.2.5.1
28、0.4 Interrupt Message Number attribute 485.2.5.11 Administrator OQ class . 485.2.5.11.1 Administrator OQ class overview . 485.2.5.11.2 Interrupt Message Number attribute 485.2.5.11.3 Element Array Address attribute 485.2.5.11.4 Element Length attribute 485.2.5.11.5 Number Of Elements attribute . 485
29、.2.5.11.6 PI Address attribute . 485.2.5.11.7 CI Address attribute . 485.2.5.12 Operational OQ class 495.2.5.12.1 Operational OQ class overview . 495.2.5.12.2 OQ ID attribute . 495.2.5.12.3 Element Array Address attribute 495.2.5.12.4 Element Length attribute 495.2.5.12.5 Number Of Elements attribut
30、e . 495.2.5.12.6 PI Address attribute . 495.2.5.12.7 CI Address attribute . 505.2.5.12.8 Minimum Coalescing Time attribute 505.2.5.12.9 Maximum Coalescing Time attribute . 505.2.5.12.10 Coalescing Count attribute 505.2.5.12.11 Wait For Rearm attribute . 505.2.5.12.12 Interrupt Message Number attribu
31、te 515.2.5.12.13 Spanning Allowed attribute 515.2.5.12.14 Queue Protocol attribute 515.3 Queuing model . 525.3.1 Queuing model overview 525.3.2 Circular queue model 525.3.2.1 Circular queue functional overview . 525.3.2.2 Relationship of IU to elements 545.3.2.3 Queue producer 545.3.2.4 Queue consum
32、er . 555.3.2.5 Enqueue operation 555.3.2.5.1 Enqueue To IQ operation overview . 555.3.2.5.2 Enqueue To OQ operation overview . 565.3.2.5.3 PQI host enqueuing IUs to an IQ . 565.3.2.5.4 PQI device enqueuing IUs to an OQ . 575.3.2.6 Dequeue operation 595.3.2.6.1 Dequeue From IQ operation overview . 59
33、5.3.2.6.2 Dequeue From OQ operation overview . 595.3.2.6.3 PQI host dequeuing IUs from an OQ . 595.3.2.6.4 PQI device dequeuing IUs from an IQ . 615.3.2.7 IU Available notification . 625.3.2.7.1 IU Available On IQ operation overview 625.3.2.7.2 IU Available On OQ operation overview 625.3.2.7.3 IU Av
34、ailable On OQ notification . 625.3.2.7.4 IU Available On IQ notification . 625.3.3 Creating circular queues . 635.3.3.1 Creating circular queues overview 635.3.3.2 Creating the administrator queue pair . 635.3.3.3 Creating operational queues . 665.3.4 Deleting circular queues . 675.3.4.1 Deleting ci
35、rcular queues overview . 675.3.4.2 Deleting the administrator queue pair . 675.3.4.3 Deleting operational queues 685.3.5 IQ priority 69iv5.4 OQ service notification methods 695.4.1 OQ service notification methods overview 695.4.2 Sending OQ service notifications in MSI-X mode . 695.4.2.1 Sending OQ
36、service notifications in MSI-X mode overview 695.4.2.2 Sending OQ service notifications for an administrator OQ 695.4.2.3 Sending OQ service notifications for an operational OQ .695.4.3 Sending OQ service notifications in legacy INTx mode 725.4.4 Sending OQ service notifications in polled mode . 735
37、.4.5 Servicing OQ service notifications in MSI-X mode . 735.4.6 Servicing OQ service notifications in legacy INTx mode 735.4.7 Servicing OQ service notifications in polled mode 735.5 PD (PQI device) state machine 745.5.1 PD (PQI device) state machine overview . 745.5.2 PD0:Power_On_And_Reset state 7
38、45.5.2.1 PD0:Power_On_And_Reset state description 745.5.2.2 Transition PD0:Power_On_And_Reset to PD1:PQI_Status_Available . 755.5.3 PD1:PQI_Status_Available state 755.5.3.1 PD1:PQI_Status_Available state description 755.5.3.2 Transition PD1:PQI_Status_Available to PD0:Power_On_And_Reset . 755.5.3.3
39、Transition PD1:PQI_Status_Available to PD2:All_Registers_Ready 755.5.3.4 Transition PD1:PQI_Status_Available to PD4:Error 755.5.4 PD2:All_Registers_Ready state 755.5.4.1 PD2:All_Registers_Ready state description 755.5.4.2 Transition PD2:All_Registers_Ready to PD0:Power_On_And_Reset 765.5.4.3 Transit
40、ion PD2:All_Registers_Ready to PD1:PQI_Status_Available 765.5.4.4 Transition PD2:All_Registers_Ready to PD3:Administrator_Queue_Pair_Ready 765.5.4.5 Transition PD2:All_Registers_Ready to PD4:Error . 765.5.5 PD3:Administrator_Queue_Pair_Ready state 765.5.5.1 PD3:Administrator_Queue_Pair_Ready state d
41、escription 765.5.5.2 Transition PD3:Administrator_Queue_Pair_Ready to PD0:Power_On_And_Reset . 765.5.5.3 Transition PD3:Administrator_Queue_Pair_Ready to PD1:PQI_Status_Available . 765.5.5.4 Transition PD3:Administrator_Queue_Pair_Ready to PD2:All_Registers_Ready 775.5.5.5 Transition PD3:Administrat
42、or_Queue_Pair_Ready to PD4:Error 775.5.6 PD4:Error state . 775.5.6.1 PD4:Error state description . 775.5.6.2 Transition PD4:Error to PD0:Power_On_And_Reset 775.5.6.3 Transition PD4:Error to PD1:PQI_Status_Available 775.6 Register based error information 785.7 PQI reset 805.7.1 PQI reset overview . 8
43、05.7.2 PQI soft reset 805.7.3 PQI firm reset 815.7.4 PQI hard reset 816 PCI Express requirements and PQI device registers . 826.1 PCI Express requirements . 826.2 PQI device memory space . 836.2.1 PQI device memory space overview . 836.2.2 PQI device standard registers . 846.2.3 PQI device assigned
44、registers 856.2.4 PQI Device Signature register 856.2.5 Administrator Queue Configuration Function register . 866.2.6 PQI Device Capability register 876.2.7 Legacy INTx Interrupt Status register . 886.2.8 Legacy INTx Interrupt Mask Set register 896.2.9 Legacy INTx Interrupt Mask Clear register . 896
45、.2.10 PQI Device Status register 90v6.2.11 Administrator IQ PI Offset register 916.2.12 Administrator OQ CI Offset register 916.2.13 Administrator IQ Element Array Address register . 926.2.14 Administrator OQ Element Array Address register . 926.2.15 Administrator IQ CI Address register 926.2.16 Adm
46、inistrator OQ PI Address register . 936.2.17 Administrator Queue Parameter register 936.2.18 PQI Device Error register 946.2.19 PQI Device Error Details register 956.2.20 PQI Device Reset register 966.2.21 PQI Device Power Action register . 977 Queuing layer . 1017.1 IQ CI, IQ PI, OQ CI, and OQ PI s
47、tructures . 1017.1.1 IQ CI dword . 1017.1.2 IQ PI register . 1017.1.3 OQ CI register . 1017.1.4 OQ PI dword . 1028 SGL (scatter gather list) . 1038.1 SGL overview . 1038.2 Standard SGL segment and last standard SGL segment 1038.3 SGL descriptors 1048.3.1 SGL descriptors overview . 1048.3.2 Data Bloc
48、k descriptor 1048.3.3 Bit Bucket descriptor . 1058.3.4 Standard SGL Segment descriptor . 1068.3.5 Last Standard SGL Segment descriptor . 1079 Common properties for all IU layers 1089.1 Overview of common properties for all IU layers 1089.2 IUs and elements . 1089.2.1 IUs and elements overview . 1089
49、.2.2 IU contained within a single element 1089.2.3 IU that spans multiple elements 1089.3 Common IU header for all IU layers . 10910 Administrator IUs and administrator functions . 11110.1 IU definition 11110.1.1 IU definition overview 11110.1.2 Administrator IU header 11210.1.3 NULL IU 11410.1.4 GENERAL ADMIN REQUEST IU . 11410.1.5 GENERAL ADMIN RESPONSE IU . 11710.1.5.1 GENERAL ADMIN RESPONSE IU overview 11710.1.5.2 Additional status descriptor for STATUS field set to DATA-IN BUFFER UNDERFLOW . 12010.1.5.3 Additional status descriptor for STATUS field set to INVALID FIELD IN REQUEST IU
