1、 TECHNICAL REPORT T1.TR.81-2003 Technical Report on Synchronization Network Architecture Prepared by T1X1.3 Working Group on Synchronization and Tributary Analysis Interfaces Problem Solvers to the Telecommunications Industry A Word from ATIS and Committee T1 Established in February 1984, Committee
2、T1 develops technical standards, reports and requirements regarding interoperability of telecommunications networks at interfaces with end-user systems, carriers, information and enhanced-service providers, and customer premises equipment (CPE). Committee T1 is sponsored by ATIS and is accredited by
3、 ANSI. T1.TR.81-2003 Published by Alliance for Telecommunications Industry Solutions 1200 G Street, NW, Suite 500 Washington, DC 20005 Committee T1 is sponsored by the Alliance for Telecommunications Industry Solutions (ATIS) and accredited by the American National Standards Institute (ANSI). Copyri
4、ght 2003 by Alliance for Telecommunications Industry Solutions All rights reserved. No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. For information contact ATIS at 202.628.6380. ATIS is
5、online at . Printed in the United States of America. T1.TR.81-2003 Technical Report on Synchronization Network Architecture Secretariat Alliance for Telecommunications Industry Solutions April 2003 American National Standards Institute, Inc. Abstract This Technical Report (TR) provides concepts and
6、techniques for synchronization architectures for use in digital communication networks. The issues and concepts associated with synchronization network architectures are discussed in detail in this report. T1.TR.81-2003 Foreword This Technical Report (TR) provides concepts and techniques for synchro
7、nization architectures for use in digital communication networks. The issues and concepts associated with synchronization network architectures are intended to provide guidance in establishing a synchronization network. This work was initiated and completed by the T1X1.3 Working Group between 1997 a
8、nd 2001. Please contact Working Group T1X1.3 to verify that the information contained in this document is current. C.A. Underkoffler, T1 Chief Editor A. Wertheimer, T1X1 Technical Editor Table of Contents 1 SCOPE, PURPOSE, AND APPLICATION 1 1.1 SCOPE.1 2 REFERENCES.1 3 DEFINITIONS 2 4 ABBREVIATIONS3
9、 5 GENERAL5 5.1 INTRODUCTION TO SYNCHRONIZATION.5 5.2 BACKGROUND ON NETWORK SYNCHRONIZATION5 5.3 FUNDAMENTALS OF SIGNAL DIGITIZATION6 5.4 PLL OPERATION.6 5.4.1 DIRECT DIGITAL SYNTHESIS .7 5.5 CLOCK PARAMETERS AND STRATUM LEVELS .8 5.5.1 STRATUM 1 AND PRS .8 5.5.2 STRATUM 2 9 5.5.3 STRATUM 3 AND 3E 9
10、 5.5.4 SONET MINIMUM CLOCK9 5.5.5 STRATUM 4 9 5.5.6 OTHER HIERARCHICAL CLOCKS10 5.6 CLOCK MODES OF OPERATION .10 5.6.1 FREE-RUN MODE 10 5.6.2 NORMAL MODE.10 5.6.3 HOLDOVER MODE .10 5.7 IMPAIRMENTS10 5.7.1 JITTER AND WANDER.10 5.7.2 TRANSIENTS .12 5.7.3 SLIP BUFFERS 14 5.7.3.1 EFFECTS OF CONTROLLED S
11、LIPS ON TRAFFIC15 5.7.3.2 POINTER JUSTIFICATION MECHANISM16 5.7.3.3 DEGRADATION CAUSED BY POINTER JUSTIFICATION .18 5.7.3.4 POINTER JUSTIFICATION COUNTS (PJCS)18 5.8 NETWORK ELEMENT SYNCHRONIZATION METHODS 18 5.8.1 INTERNAL TIMING 18 5.8.2 LOOP TIMING18 5.8.3 EXTERNAL TIMING.19 5.8.4 LINE TIMING .19
12、 5.8.5 THROUGH TIMING20 5.8.6 SONET RINGS 20 5.9 BUILDING INTEGRATED TIMING SUPPLIES (BITS) .21 5.9.1 THE BITS CONCEPT .21 5.9.2 THE TIMING SIGNAL GENERATOR .22 ii T1.TR.81-2003 6 ARCHITECTURE METHODS 23 6.1 HIERARCHICAL23 6.1.2 HIERARCHY CLOCK REQUIREMENTS24 6.2 DISTRIBUTION.25 6.3 SONET.25 6.4 PLE
13、SIOCHRONOUS STRATUM 1.27 6.4.1 PRIMARY REFERENCE SOURCES 27 6.4.2 PRS DEPLOYMENT PHILOSOPHIES .28 6.4.3 MULTIPLE TIMING ISLAND OPERATION.29 6.4.4 PRS IN ALMOST EVERY BUILDING .29 7 SYNCHRONIZATION SIGNALS30 7.1 COMPOSITE CLOCK (CC) SIGNAL.30 7.2 DS1 TIMING SIGNAL .31 7.3 SONET DERIVED DS1 .32 8 ENGI
14、NEERING CONSIDERATIONS.33 8.1 INTRA-BUILDING 33 8.2 INTER-BUILDING 33 8.3 TIMING LOOPS 34 8.4 DIVERSITY / SURVIVABILITY35 8.4.1 INTER-OFFICE TRANSPORT 36 8.4.2 REDUNDANT FEEDS.36 8.4.3 ROUTE DIVERSITY.36 8.4.4 SIGNAL AVAILABILITY.36 8.4.5 REDUNDANT INTERNAL CLOCK UNITS36 8.4.6 CONSTRAINTS ON TRANSIE
15、NT GENERATION.36 9 PERFORMANCE CHARACTERIZATION AND MONITORING.36 9.1 WANDER PARAMETERS37 9.2 STS-1 AND VT1.5 POINTER JUSTIFICATION COUNTS (PJC).38 A COMPARISON OF ANSI AND ITU-T CLOCK SPECIFICATIONS40 B AN EFFICIENT METHOD FOR CALCULATING TDEV 41 B.1 DESIGN OF TDEV ALGORITHMS .41 B.1.1 TDEV DEFINIT
16、ION 41 B.1.2 STANDARD ALGORITHM .41 B.2 EFFICIENT ALGORITHM 43 B.2.1 TYPE I DEVIATION .43 B.2.2 TYPE II DEVIATION 44 B.2.3 NOTES ON THE PSEUDO-CODE:.45 B.3 PSEUDO-CODE FOR THE ALGORITHMS: 45 B.3.1 PSEUDO-CODE FOR STANDARD ALGORITHM:.45 B.3.2 PSEUDO-CODE FOR EFFICIENT ALGORITHM:46 Table of Tables TAB
17、LE 1 - EFFECT OF SLIPS ON TRAFFIC16 TABLE 2 - STRATUM LEVEL SPECIFICATIONS .25 TABLE 3 - POTENTIAL FACILITIES AS TIMING PATHS AND THEIR PREFERENCE WEIGHTING .34 TABLE A.1 - SUMMARY OF SOME PARAMETERS FOR ANSI AND ITU-T CLOCK SPECIFICATIONS (FROM T1.101-1999).40 Table of Figures FIGURE 1 - A GENERIC
18、PHASE LOCKED LOOP .6 FIGURE 2 - DIRECT DIGITAL SYNTHESIS GENERIC BLOCK DIAGRAM.7 FIGURE 3 - JITTER AND WANDER IN THE FREQUENCY DOMAIN.12 iii T1.TR.81-2003 FIGURE 4 - PHASE TRANSIENT IN TIME DOMAIN AND THE PHASE PLOT.13 FIGURE 5 - DS1 SLIP BUFFER FUNCTIONAL BLOCK DIAGRAM .14 FIGURE 6 - SONET FRAME AR
19、RANGEMENT WITH POINTER MECHANISM17 FIGURE 7 - INTERNAL TIMING .18 FIGURE 8 - LOOP TIMING.19 FIGURE 9 - EXTERNAL TIMING19 FIGURE 10 - LINE TIMING 20 FIGURE 11 - THROUGH TIMING.20 FIGURE 12 - RING TIMING .21 FIGURE 13 - THE BITS CONCEPT IN BLOCK DIAGRAM REPRESENTATION.22 FIGURE 14 - PRIORITY MASTER-SL
20、AVE HIERARCHY FOR TIMING DISTRIBUTION 24 FIGURE 15 - EXAMPLE OF SYNCHRONIZATION OF SONET RING .27 FIGURE 16 - EXAMPLE OF SYNCHRONIZATION DISTRIBUTION, PRS IN ALMOST EVERY BUILDING30 FIGURE 17 - CC SIGNAL .31 FIGURE 18 - DS1 TIMING SIGNAL 31 FIGURE 19 - DERIVED DS1 TIMING PATH IN SONET EQUIPMENT CO-L
21、OCATED WITH A BITS 33 FIGURE 20 - ILLUSTRATION OF TIMING LOOP CREATION35 FIGURE 21 - TIME INTERVAL ERROR (TIE) 37 FIGURE 22 - MAXIMUM TIME INTERVAL ERROR (MTIE) REQUIREMENT FOR TIMING SIGNALS .38 FIGURE 23 - MEAN-TIME BETWEEN POINTERS FOR CLOCK FREQUENCY OFFSET39 iv T1.TR.81-2003 Technical Report on
22、 Synchronization Network Architecture 1 Scope, Purpose, and Application 1.1 Scope This Technical Report (TR) encompasses the principles, methods, guidelines, and components that form the building blocks of synchronization architectures in modern digital telecommunications networks. The detailed tech
23、nical requirements and specifications governing such timing distribution sub-systems are given in the many different industry standards listed in clause 2, but the body of knowledge that is needed to apply these specifications to actual networks capable of robust synchronous operation is not collect
24、ed in a single document. This lack of a resource for synchronization network designers has been recognized by T1X1.3 and is addressed by this report. Other “network timing” topics, such as time-of-day distribution including Network Timing Protocol (NTP) for example are not addressed. 2 References T1
25、.101-1999, Synchronization Interface Standard.1T1.102-1993 (R1999), Digital Hierarchy Electrical Interfaces.1T1.105-2001, Digital Hierarchy Optical Interfaces Rates and Formats Specifications (SONET).1T1.105.03-2003, Synchronous Optical Network (SONET Jitter at Network Interfaces.1T1.105.09-1996 (R2
26、002), Synchronous Optical Network (SONET) - Network Element Timing and Synchronization.1T1.231-1997, Digital Hierarchy - Layer 1 in-Service Digital Transmission Performance Monitoring.1T1.523-2001, Telecom Glossary 2000.1GR-253-CORE, Issue 3, September 2000, Synchronous Optical Network (SONET) Trans
27、port Systems: Common Generic Criteria.2GR-378-CORE, Issue 2, February 1999, Generic Requirements for Timing Signal Generators.2GR-436-CORE, Issue 1 Revision 1, June 1996, Digital Network Synchronization Plan.2GR-1244-CORE, Issue 2, December 2000, Clocks for the Synchronized Network: Common Generic C
28、riteria.2GR-2830-CORE, Issue 2, December 1995, Primary Reference Sources: Generic Criteria.2ITU-T Recommendation G.781, Synchronization layer functions.3ITU-T Recommendation G.810, Definitions and terminology for synchronization networks.3ITU-T Recommendation G.811, Timing characteristics of primary
29、 reference clocks.31This document is available from the Alliance for Telecommunications Industry Solutions . 2This document is available from Telcordia Technologies . 3This document is available from the ITU-T . 1 T1.TR.81-2003 ITU-T Recommendation G.812, Timing requirements of slave clocks suitable
30、 for use as node clocks in synchronization networks.3ITU-T Recommendation G.813, Timing characteristics of SDH equipment slave clocks (SEC).3ITU-T RECOMMENDATION G.822, CONTROLLED SLIP RATE OBJECTIVES ON AN INTERNATIONAL DIGITAL CONNECTION.3ITU-T Recommendation G.824, The control of jitter and wande
31、r within digital networks which are based on the 1544 kbits/s hierarchy.3ITU-T Recommendation G.825, The control of jitter and wander within digital networks which are based on the SDH hierarchy.3ITU-T Recommendation O.172, Jitter and wander measuring equipment for digital systems which are based on
32、 the synchronous digital hierarchy (SDH).3IEEE PP 4148, 1999, DIRECT DIGITAL FREQUENCY SYNTHESIZERS, ISBN078033438-8. 3 Definitions 3.1 Asynchronous: In the context of this TR, asynchronous signals or equipment have a source of clocking that is not traceable to a network clock (PRS). This source is
33、typically a free-running crystal oscillator in a network element that is not required to be network-synchronous. For example, a DS3 signal used to transport DS1 signals between offices is usually asynchronous, because the DS1s are individually pulse-stuffed into the DS3 carrier for regeneration at t
34、he termination in a frequency-transparent mode. 3.2 Jitter: As defined in T1.101-1999 and other industry standards, jitter on a digital bit-stream is phase variation from the ideal in the frequency range above 10 Hz. The upper frequency limit is specified for different signals in T1.102-1993 (R1999)
35、 and T1.105.03-2003. Jitter on a received signal may cause bit errors by excessively offsetting the sampled bits in the receiver relative to the recovered (sampling) clock. Jitter is usually characterized as a peak-to-peak range of phase deviation expressed in Unit Intervals (UI), where 1 UI is the
36、inverse of the signals symbol-rate. 3.3 Plesiochronous: Two digital networks that are timed by different PRSs may interchange data streams with a very low chance of a slip, because of the very high accuracy of the PRS as specified in T1.101-1999 and G.811. This is the plesiochronous mode of operatio
37、n defined in T1.101-1999 and is very common in todays digital networks. NOTE - The term Plesiochronous Digital Hierarchy (PDH) is used in some documents to refer to the family of asynchronously multiplexed hierarchy of signals described in T1.102-1993 (R1999) and ITU-T Recommendation G.702. This is
38、inconsistent with the above definition of plesiochronous operation. 3.4 Synchronization: The process of timing telecommunications switching, transport, etc., functions and operations by the same master clock or system of master clocks.4It literally means “same time” and conveys the meaning that time
39、, frequency deviation, and phase deviation are zero or aligned. The term “syntonization” literally means same tone or frequency, and refers to systems operating at the same frequency, but not necessarily the same phase. The term “synchronization” has been embraced by the industry to refer to both ca
40、ses, and will be used in this document. 3.5 Synchronous: Signals and network elements are defined as synchronous if they are timed by clock signals that are derived from a common reference source - the PRS or “network clock.” Note that timing signals have different frequencies to match the traffic s
41、ignal, but the different frequencies are all traceable to the PRS through digital multiplier or divider hardware as required. 4For examples, see T1.101-1999 for specification of a PRS. 2 T1.TR.81-2003 3.6 Traceable: The process of distributing clocking frequencies by master-slave chains ensures that
42、 the accuracy of the first clock in the chain is replicated at the last clock and each one in between (assuming fault-free conditions). Thus, all the signals timed by all the clocks are “traceable” to the first clock. 3.7 Timing Island: A “timing island” consists of a master timing reference source
43、and all the signals and equipment that have timing traceable to it. Thus, a PRS and the network elements subtended from it, regardless of architecture or technologies, form a timing island. In a network with a fault condition causing a BITS to operate in holdover mode, the BITS and its subtended equ
44、ipment form a temporary timing island. 3.8 Coordinated Universal Time (UTC): UTC is the time scale maintained by the International Bureau of Weights and Measures (BIPM)5with the cooperation of international agencies including the US Naval Observatory and the National Institute of Standards and Techn
45、ology (NIST). It is the standard official time-of-day and forms the basis of a coordinated dissemination of standard frequencies and time-of-day signals. UTC is coordinated to stay within 1 second of astronomical time through the insertion of leap seconds. UTC is post-processed and determined severa
46、l weeks after measurements are made. Many national atomic clock based time-of-day and frequency standards (such as the ones at NIST in Boulder, CO) are compared and a virtual time-of-day and frequency standard based on their averages is calculated monthly. Corrections are then made to the real-time
47、national standards. 3.9 Wander: As defined in T1.101-1999 and other industry standards, wander on a digital bit-stream is phase variation from the ideal in the frequency range from DC to 10 Hz. Wander on a received signal will cause buffer spills in receiving equipment if the wander exceeds the capa
48、city of the buffer. 4 Abbreviations ADM Add-Drop Multiplexer ADPCM Adaptive Differential Pulse Code Modulation AIS Alarm Indication Signal BIPM International Bureau of Weights and Measures BITS Building Integrated Timing Supply BPV BiPolar Violation CC Composite ClockCPE Customer Premises Equipment
49、CRC Cyclic Redundancy Check DDS Digital Data Service DDS Direct Digital Synthesis DLC Digital Loop Carrier DPLL Digital Phase-Locked Loop DS0 Digital Signal, level 0 DS1 Digital Signal, level 1 DS3 Digital Signal, level 3 DSX1 Digital Signal Cross-connect at DS1 DUS Do not Use for Sync ESF Extended Superframe Format (DS1) ESI External Synchronization Interface 5T.J Quinn, “The BIPM and the accurate measurement of time,” Proc. IEEE, vol. 79, pp 894-905, 1991. 3 T1.TR.81-2003 GPS Global Positioning System Hz Hertz LEC Local Exchange Carrier LNC Local Node Clocks LORAN-C LOng R
