1、BRITISH STANDARD BS EN 60191-6-6:2001 IEC 60191-6-6:2001 Mechanical standardization of semiconductor devices Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for fine pitch land grid array (FLGA) The European Standard EN 60
2、191-6-6:2001 has the status of a British Standard ICS 31.080.10; 01.100.25 NO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBS EN 60191-6-6:2001 This British Standard, having been prepared under the direction of the Electrotechnical Sector Policy and Strategy Committee, was publ
3、ished under the authority of the Standards Policy and Strategy Committee on 5 September 2001 BSI 5 September 2001 ISBN 0 580 38393 8 National foreword This British Standard is the official English language version of EN 60191-6-6:2001. It is identical with IEC 60191-6-6:2001. The UK participation in
4、 its preparation was entrusted by Technical Committee EPL/47, Semiconductor devices, to Subcommittee EPL/47/4, Mechanical standardization of semiconductor devices, which has the responsibility to: A list of organizations represented on this committee can be obtained on request to its secretary. From
5、 1 January 1997, all IEC publications have the number 60000 added to the old number. For instance, IEC 27-1 has been renumbered as IEC 60027-1. For a period of time during the change over from one numbering system to the other, publications may contain identifiers from both systems. Cross-references
6、 The British Standards which implement international or European publications referred to in this document may be found in the BSI Standards Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Find” facility of the BSI Standards Electronic Catalogue.
7、 A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. aid enquirers to understand the text; pr
8、esent to the responsible international/European committee any enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. Summary of pages This document comprises a front cover, a
9、n inside front cover, the EN title page, pages 2 to 13 and a back cover. The BSI copyright date displayed in this document indicates when the document was last issued. Amendments issued since publication Amd. No. Date CommentsEUROPEAN STANDARD EN 60191-6-6 NORME EUROPENNE EUROPISCHE NORM July 2001 C
10、ENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels 2001 CENELEC - All rights of exploitation in any form and by any means reserved w
11、orldwide for CENELEC members. Ref. No. EN 60191-6-6:2001 E ICS 31.080.01 English version Mechanical standardization of semiconductor devices Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine pitch land grid array
12、(FLGA) (IEC 60191-6-6:2001) Normalisation mcanique des dispositifs semi-conducteurs Partie 6-6: Rgles gnrales pour la prparation des dessins dencombrement des dispositifs semiconducteurs pour montage en surface - Guide de conception des dispositifs FLGA (CEI 60191-6-6:2001) Mechanische Normung von H
13、albleiterbauelementen Teil 6-6: Allgemeine Regeln fr die Erstellung von Gehusezeichnungen von SMD-Halbleitergehusen - Konstruktionsleitfaden fr Feinraster- Land-Grid-Array (FLGA) (IEC 60191-6-6:2001) This European Standard was approved by CENELEC on 2001-05-01. CENELEC members are bound to comply wi
14、th the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretar
15、iat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the
16、official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom.Foreword The text of docum
17、ent 47D/404/FDIS, future edition 1 of IEC 60191-6-6, prepared by SC 47D, Mechanical standardization of semiconductor devices, of IEC TC 47, Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 60191-6-6 on 2001-05-01. The following dates were fixed:
18、 latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2002-02-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2004-05-01 Annexes designated “normative“ are part o
19、f the body of the standard. In this standard, annex ZA is normative. Annex ZA has been added by CENELEC. _ Endorsement notice The text of the International Standard IEC 60191-6-6:2001 was approved by CENELEC as a European Standard without any modification. _ EN6019166:20012 BSI 5 September 2001 INTR
20、ODUCTION The demand for area array style packages exists because of the multi-functions and high performance of electrical equipment. The objective of this design guide is to standardize outlines and to get interchangeability of FLGA packages. The terminal pitch and package outlines of these fine-pi
21、tch array packages are smaller than those of LGA packages. EN6019166:20013 BSI 5 September 2001 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for fine-pitch land grid a
22、rray (FLGA) 1 Scope This part of IEC 60191 provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch land grid array (hereinafter called FLGA) whose terminal pitch is less than, or equal to, 0,80 mm and whose package body outline is square. 2 No
23、rmative references The following normative documents contain provisions which, through reference in this text, constitute provisions of this part of IEC 60191. For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements base
24、d on this part of IEC 60191 are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references, the latest edition of the normative document referred to applies. Members of IEC and ISO maintain registers of currently
25、valid International Standards. IEC 60191 (all parts), Mechanical standardization of semiconductor devices 3 Definitions For the purposes of this part of IEC 60191, the following definitions, as well as those given in the other parts of this standard, apply. 3.1 flanged type type whose package body s
26、ize (body length and width) consists of its own flange composed around the encapsulation or lid 3.2 type of real chip size type whose package body size (body length and width) consists of an encapsulation around the real chip only 3.3 FLGA packages with metal lands or metal bumps of which the termin
27、al height is less than, or equal to, 100 m, and whose terminal pitch is less than, or equal to, 0,80 mm, positioned in an array on the base plane of the package as external terminals This package structure makes it possible to surface-mount the packages to the printed circuit board EN6019166:20014 B
28、SI 5 September 2001 3.4 material designation FLGA packages are classified according to the following two material designations: 3.4.1 plastic type (P-FLGA) plastic-type classification is assigned to packages which consist of resin substrate as interposer material (for example, glass-epoxy, poly-imid
29、) 3.4.2 ceramic type (C-FLGA) ceramic-type classification is assigned to packages which consist of ceramic substrate as interposer material EN6019166:20015 BSI 5 September 2001 A1 A2 Even type Odd type A2 A1 nE nD D E w SA w SB v 4 A B e e ZE b SD ZD 123 A B C SE S x M A3 A4 B1 B2 B3 B4 A1 A2 S Note
30、 1 y1 S y A1 A S Seating plane Note 2 Note 2 Note 3 Design guide for Fine-pitch land grid array family IEC 60191 Design guide for fine-pitch land grid array family IEC 300/01 EN6019166:20016 BSI 5 September 2001 NOTE 1 Zone of a visible index on the top surface. NOTE 2 Datum A and B are the axes def
31、ined by the terminal positions indicated with datum targets. NOTE 3 Primary datum S and seating plane to be defined by the method of least squares of spherical crowns of terminals. EN6019166:20017 BSI 5 September 2001 Table 1 Group 1: Dimensions appropriate to mounting and interchangeability Limits
32、to be observed Ref. Min. Nom. Max. Recommended values for the dimensions mm Note nX 1, 2 nD X 1 nE X A X A max. = 1,20, 1,70, 2,00 Includes heat slug Includes package warpage and tilt A 1 XA 1max. = 0,10 b X X X At ceramic FLGA (C-FLGA) Min. Nom. Max. at e = 0,80 0,45 0,50 0,55 at e = 0,65 0,35 0,40
33、 0,45 at e = 0,50 0,25 0,30 0,35 at e = 0,40 0,20 0,25 0,30 At plastic FLGA (P-FLGA) Min. Nom. Max. at e = 0,80 0,35 0,40 0,45 at e = 0,65 0,28 0,33 0,38 at e = 0,50 0,20 0,25 0,30 at e = 0,40 0,15 0,20 0,25 D X At flanged type D = 4,0, 5,0, 6,0, 7,0, 8,0, 9,0, 10,0, 11,0, 12,0, 13,0, 14,0, 15,0, 16
34、,0, 17,0, 18,0, 19,0, 20,0, 21,0 At type of real chip size D = from 3,1 to 21,0 Dimension range shows nominal value E X At flanged type E = 4,0, 5,0, 6,0, 7,0, 8,0, 9,0, 10,0, 11,0, 12,0, 13,0, 14,0, 15,0, 16,0, 17,0, 18,0, 19,0, 20,0, 21,0 At type of real chip size E = from 3,1 to 21,0 Dimension ra
35、nge shows nominal value e X e = 0,80, 0,65, 0,50, 0,40 v X v = 0,15 Includes burrs w X at e = 0,80 w = 0,20 at e = 0,65 w = 0,20 at e = 0,50 w = 0,20 at e = 0,40 w = 0,15 x X at e = 0,80 x = 0,08 at e = 0,65 x = 0,08 at e = 0,50 x = 0,05 at e = 0,40 x = 0,05 EN6019166:20018 BSI 5 September 2001 Tabl
36、e 1 (continued) Limits to be observed Ref. Min. Nom. Max. Recommended values for the dimensions mm Note y X at e = 0,80 y = 0,10 at e = 0,65 y = 0,10 at e = 0,50 y = 0,08 at e = 0,40 y = 0,08 y 1 Xy 1 = 0,2 NOTE 1 The values stipulated by the mathematical expression should be applied to the individu
37、al overall dimensional standards. NOTE 2 Symbol n refers to the total number of terminal positions. Table 2 Group 2: Dimensions appropriate to mounting and gauging Limits to be observed Ref. Min. Nom. Max. Recommended values for the dimensions mm Note b2 X At ceramic FLGA (C-FLGA) at e = 0,80 b2 = 0
38、,63 at e = 0,65 b2 = 0,53 at e = 0,50 b2 = 0,40 at e = 0,40 b2 = 0,35 At plastic FLGA (P-FLGA) at e = 0,80 b2 = 0,53 at e = 0,65 b2 = 0,46 at e = 0,50 b2 = 0,35 at e = 0,40 b2 = 0,30 e X e = 0,80, 0,65, 0,50, 0,40 eD X eD = e x (nD 1) 1 a eE X eE = e x (nE 1) aSee note 1 of table 1. EN6019166:20019
39、BSI 5 September 2001 Table 3 Group 3: Dimensions appropriate to automated handling Limits to be observed Ref. Min. Nom. Max. Recommended values for the dimensions mm Note A X A max. = 1,20, 1,70, 2,00 Includes heat slug Includes package warpage and tilt D X D/E = 4,0, 5,0, 6,0, 7,0, 8,0, 9,0, 10,0,
40、11,0, 12,0, 13,0, 14,0, 15,0, 16,0, E X 17,0, 18,0, 19,0, 20,0, 21,0 y 1 Xy 1= 0,2 Table 4 Group 4: Dimensions for information only Limits to be observed Ref. Min. Nom. Max. Recommended values for the dimensions mm Note ZD X ZD = (D e (nD 1)/2 1a ZE X ZE = (E e (nE 1)/2 aSee note 1 of table 1. EN601
41、9166:200110 BSI 5 September 2001 Table 5 Dimensions and ball matrix e = 0,80 Maximum matrix row family Maximum matrix 1 row family Maximum matrix 2 row family E D nD nE n ZD ZE nD nE n ZD ZE nD nE n ZD ZE 4 4 4 4 16 0,80 0,80 3 3 9 1,20 1,20 5 5 6 6 36 0,50 0,50 5 5 25 0,90 0,90 4 4 16 1,30 1,30 6 6
42、 7 7 49 0,60 0,60 6 6 36 1,00 1,00 7 7 8 8 64 0,70 0,70 7 7 49 1,10 1,10 8 8 9 9 81 0,80 0,80 8 8 64 1,20 1,20 9 9 11 11 121 0,50 0,50 10 10 100 0,90 0,90 9 9 81 1,30 1,30 10 10 12 12 144 0,60 0,60 11 11 121 1,00 1,00 11 11 13 13 169 0,70 0,70 12 12 144 1,10 1,10 12 12 14 14 196 0,80 0,80 13 13 169
43、1,20 1,20 13 13 16 16 256 0,50 0,50 15 15 225 0,90 0,90 14 14 196 1,30 1,30 14 14 17 17 289 0,60 0,60 16 16 256 1,00 1,00 15 15 18 18 324 0,70 0,70 17 17 289 1,10 1,10 16 16 19 19 361 0,80 0,80 18 18 324 1,20 1,20 17 17 21 21 441 0,50 0,50 20 20 400 0,90 0,90 19 19 361 1,30 1,30 18 18 22 22 484 0,60
44、 0,60 21 21 441 1,00 1,00 19 19 23 23 529 0,70 0,70 22 22 484 1,10 1,10 20 20 24 24 576 0,80 0,80 23 23 529 1,20 1,20 21 21 26 26 676 0,50 0,50 25 25 625 0,90 0,90 24 24 576 1,30 1,30 e = 0,65 Maximum matrix row family Maximum matrix 1 row family Maximum matrix 2 row family E D nD nE n ZD ZE nD nE n
45、 ZD ZE nD nE n ZD ZE 4 4 5 5 25 0,700 0,700 4 4 16 1,025 1,025 5 5 7 7 49 0,550 0,550 6 6 36 0,875 0,875 6 6 8 8 64 0,725 0,725 7 7 49 1,050 1,050 7 7 10 10 100 0,575 0,575 9 9 81 0,900 0,900 8 8 11 11 121 0,750 0,750 10 10 100 1,075 1,075 9 9 13 13 169 0,600 0,600 12 12 144 0,925 0,925 10 10 15 15
46、225 0,450 0,450 14 14 196 0,775 0,775 13 13 169 1,100 1,100 11 11 16 16 256 0,625 0,625 15 15 225 0,950 0,950 12 12 18 18 324 0,475 0,475 17 17 289 0,800 0,800 16 16 256 1,125 1,125 13 13 19 19 361 0,650 0,650 18 18 324 0,975 0,975 14 14 21 21 441 0,500 0,500 20 20 400 0,825 0,825 19 19 361 1,150 1,
47、150 15 15 22 22 484 0,675 0,675 21 21 441 1,000 1,000 16 16 24 24 576 0,525 0,525 23 23 529 0,850 0,850 22 22 484 1,175 1,175 17 17 25 25 625 0,700 0,700 24 24 576 1,025 1,025 18 18 27 27 729 0,550 0,550 26 26 676 0,875 0,875 19 19 28 28 784 0,725 0,725 27 27 729 1,050 1,050 20 20 30 30 900 0,575 0,
48、575 29 29 841 0,900 0,900 21 21 31 31 961 0,750 0,750 30 30 900 1,075 1,075 EN6019166:200111 BSI 5 September 2001 Table 5 (continued) e = 0,50 Maximum matrix row family Maximum matrix 1 row family Maximum matrix 2 row family E D nD nE n ZD ZE nD nE n ZD ZE nD nE n ZD ZE 4 4 7 7 49 0,50 0,50 6 6 36 0,75 0,75 5 5 9 9 81 0,50 0,50 8 8 64 0,75 0,75 6 6 11 11
