1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI Standards PublicationSystemVerilog Unified Hardware Design, Specification and Verification LanguageBS IEC 62530:2011National forewordThis British Standard is the UK implementation of IEC 62530:2011.
2、It super-sedes BS IEC 62530:2007 which is withdrawn.The UK participation in its preparation was entrusted to Technical CommitteeGEL/93, Design automation.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all
3、the necessary provisions of acontract. Users are responsible for its correct application. BSI 2011ISBN 978 0 580 75663 4ICS 25.040.01; 35.060Compliance with a British Standard cannot confer immunity fromlegal obligations.This British Standard was published under the authority of the StandardsPolicy
4、and Strategy Committee on 31 July 2011.Amendments issued since publicationAmd. No. Date Text affectedBRITISH STANDARDBS IEC 62530:2011IEC 62530Edition 2.0 2011-05INTERNATIONAL STANDARD SystemVerilog Unified Hardware Design, Specification, and Verification Language INTERNATIONAL ELECTROTECHNICAL COMM
5、ISSION XXICS 25.040 PRICE CODEISBN 978-2-88912-450-3IEEE Std 1800colourinsideBS IEC 62530:2011- i - IEC 62530:2011(E)IEEE Std 1800-2009Published by IEC under license from IEEE. 2009 IEEE. All rights reserved.Contents Part One: Design and Verification Constructs1. Overview 21.1 Scope 21.2 Purpose. 21
6、.3 Merger of IEEE Std 1364-2005 and IEEE Std 1800-2005 31.4 Special terms 31.5 Conventions used in this standard 31.6 Syntactic description 41.7 Use of color in this standard 51.8 Contents of this standard 51.9 Deprecated clauses. 81.10 Examples 81.11 Prerequisites. 82. Normative references. 93. Des
7、ign and verification building blocks 113.1 General. 113.2 Design elements. 113.3 Modules 113.4 Programs 123.5 Interfaces 133.6 Checkers. 143.7 Primitives . 143.8 Subroutines 143.9 Packages. 143.10 Configurations 153.11 Overview of hierarchy . 153.12 Compilation and elaboration 163.13 Name spaces. 18
8、3.14 Simulation time units and precision. 194. Scheduling semantics. 234.1 General. 234.2 Execution of a hardware model and its verification environment . 234.3 Event simulation 234.4 The stratified event scheduler 244.5 The SystemVerilog simulation reference algorithm 294.6 Determinism. 294.7 Nonde
9、terminism. 304.8 Race conditions 304.9 Scheduling implication of assignments . 304.10 The PLI callback control points. 325. Lexical conventions . 335.1 General. 335.2 Lexical tokens 335.3 White space 335.4 Comments 335.5 Operators 335.6 Identifiers, keywords, and system names 345.7 Numbers. 355.8 Ti
10、me literals . 40BS IEC 62530:2011IEC 62530:2011(E) - ii - IEEE Std 1800-2009Published by IEC under license from IEEE. 2009 IEEE. All rights reserved.5.9 String literals 405.10 Structure literals. 425.11 Array literals 435.12 Attributes 435.13 Built-in methods 456. Data types. 476.1 General. 476.2 Da
11、ta types and data objects 476.3 Value set. 476.4 Singular and aggregate types . 486.5 Nets and variables 496.6 Net types 506.7 Net declarations . 566.8 Variable declarations . 586.9 Vector declarations 606.10 Implicit declarations. 616.11 Integer data types . 626.12 Real, shortreal and realtime data
12、 types 636.13 Void data type 636.14 Chandle data type. 636.15 Class. 646.16 String data type 646.17 Event data type. 696.18 User-defined types . 706.19 Enumerations . 716.20 Constants 776.21 Scope and lifetime 846.22 Type compatibility. 866.23 Type operator. 896.24 Casting . 907. Aggregate data type
13、s 977.1 General. 977.2 Structures . 977.3 Unions 997.4 Packed and unpacked arrays 1027.5 Dynamic arrays 1067.6 Array assignments 1097.7 Arrays as arguments to subroutines . 1107.8 Associative arrays 1117.9 Associative array methods . 1147.10 Queues 1177.11 Array querying functions . 1217.12 Array ma
14、nipulation methods 1218. Classes 1278.1 General. 1278.2 Overview 1278.3 Syntax 1288.4 Objects (class instance) 1298.5 Object properties and object parameter data 1308.6 Object methods 1308.7 Constructors . 1318.8 Static class properties. 1328.9 Static methods 133BS IEC 62530:2011- iii - IEC 62530:20
15、11(E)IEEE Std 1800-2009Published by IEC under license from IEEE. 2009 IEEE. All rights reserved.8.10 This 1338.11 Assignment, renaming, and copying 1348.12 Inheritance and subclasses . 1358.13 Overridden members 1368.14 Super 1378.15 Casting . 1378.16 Chaining constructors 1388.17 Data hiding and en
16、capsulation. 1388.18 Constant class properties 1398.19 Virtual methods 1408.20 Abstract classes and pure virtual methods. 1418.21 Polymorphism: dynamic method lookup. 1418.22 Class scope resolution operator : 1428.23 Out-of-block declarations 1448.24 Parameterized classes. 1458.25 Typedef class . 14
17、88.26 Classes and structures 1498.27 Memory management 1499. Processes 1519.1 General. 1519.2 Structured procedures 1519.3 Block statements 1559.4 Procedural timing controls. 1619.5 Process execution threads 1709.6 Process control. 1719.7 Fine-grain process control 17510. Assignment statements. 1771
18、0.1 General. 17710.2 Overview 17710.3 Continuous assignments 17810.4 Procedural assignments 18110.5 Variable declaration assignment (variable initialization) 18610.6 Procedural continuous assignments . 18610.7 Assignment extension and truncation 18810.8 Assignment-like contexts. 18910.9 Assignment p
19、atterns. 19010.10 Unpacked array concatenation. 19410.11 Net aliasing 19711. Operators and expressions . 19911.1 General. 19911.2 Overview 19911.3 Operators 20011.4 Operator descriptions. 20411.5 Operands 22411.6 Expression bit lengths 22711.7 Signed expressions. 23011.8 Expression evaluation rules
20、. 23111.9 Tagged union expressions and member access 23211.10 String literal expressions 23411.11 Operator overloading . 23511.12 Minimum, typical, and maximum delay expressions 23711.13 Let construct. 23812. Procedural programming statements 245BS IEC 62530:2011IEC 62530:2011(E) - iv - IEEE Std 180
21、0-2009Published by IEC under license from IEEE. 2009 IEEE. All rights reserved.12.1 General. 24512.2 Overview 24512.3 Syntax 24512.4 Conditional ifelse statement. 24612.5 Case statement . 25112.6 Pattern matching conditional statements . 25612.7 Loop statements . 26012.8 Jump statements. 26413. Task
22、s and functions (subroutines) . 26713.1 General. 26713.2 Overview 26713.3 Tasks 26713.4 Functions 27113.5 Subroutine calls and argument passing 27713.6 Import and export functions. 28213.7 Task and function names . 28214. Clocking blocks . 28314.1 General. 28314.2 Overview 28314.3 Clocking block dec
23、laration 28314.4 Input and output skews 28514.5 Hierarchical expressions 28614.6 Signals in multiple clocking blocks . 28714.7 Clocking block scope and lifetime. 28714.8 Multiple clocking blocks example. 28714.9 Interfaces and clocking blocks. 28814.10 Clocking block events 28914.11 Cycle delay: # 2
24、8914.12 Default clocking. 29014.13 Input sampling . 29114.14 Global clocking 29214.15 Synchronous events . 29314.16 Synchronous drives 29315. Interprocess synchronization and communication. 29915.1 General. 29915.2 Overview 29915.3 Semaphores 29915.4 Mailboxes. 30115.5 Named events. 30416. Assertion
25、s. 30916.1 General. 30916.2 Overview 30916.3 Immediate assertions 30916.4 Deferred assertions. 31216.5 Concurrent assertions overview. 31616.6 Boolean expressions. 31816.7 Sequences. 32016.8 Declaring sequences. 32316.9 Sequence operations. 33116.10 Local variables. 35316.11 Calling subroutines on m
26、atch of a sequence 35916.12 System functions 36016.13 Declaring properties. 360BS IEC 62530:2011- v - IEC 62530:2011(E)IEEE Std 1800-2009Published by IEC under license from IEEE. 2009 IEEE. All rights reserved.16.14 Multiclock support. 38516.15 Concurrent assertions. 39316.16 Disable iff resolution
27、41016.17 Clock resolution. 41216.18 Expect statement 41716.19 Clocking blocks and concurrent assertions 41917. Checkers. 42117.1 Overview 42117.2 Checker declaration . 42117.3 Checker instantiation . 42417.4 Context inference. 42717.5 Checker procedures 42717.6 Covergroups in checkers 42817.7 Checke
28、r variables. 42917.8 Functions in checkers. 43517.9 Complex checker example. 43518. Constrained random value generation . 43718.1 General. 43718.2 Overview 43718.3 Concepts and usage 43718.4 Random variables. 44018.5 Constraint blocks . 44218.6 Randomization methods. 45718.7 In-line constraintsrando
29、mize() with. 45918.8 Disabling random variables with rand_mode() 46118.9 Controlling constraints with constraint_mode() 46318.10 Dynamic constraint modification. 46418.11 In-line random variable control . 46418.12 Randomization of scope variablesstd:randomize(). 46518.13 Random number system functio
30、ns and methods . 46718.14 Random stability 46818.15 Manually seeding randomize . 47118.16 Random weighted caserandcase 47118.17 Random sequence generationrandsequence. 47219. Functional coverage. 48319.1 General. 48319.2 Overview 48319.3 Defining the coverage model: covergroup. 48419.4 Using covergr
31、oup in classes. 48619.5 Defining coverage points . 48819.6 Defining cross coverage. 49819.7 Specifying coverage options 50319.8 Predefined coverage methods 50719.9 Predefined coverage system tasks and system functions. 50919.10 Organization of option and type_option members. 50919.11 Coverage comput
32、ation . 51020. Utility system tasks and system functions . 51520.1 General. 51520.2 Simulation control system tasks 51620.3 Simulation time system functions 51620.4 Timescale system tasks 51820.5 Conversion functions . 52120.6 Data query functions 522BS IEC 62530:2011IEC 62530:2011(E) - vi - IEEE St
33、d 1800-2009Published by IEC under license from IEEE. 2009 IEEE. All rights reserved.20.7 Array querying functions . 52420.8 Math functions . 52620.9 Severity tasks . 52820.10 Elaboration system tasks 52820.11 Assertion control system tasks. 53020.12 Assertion action control system tasks 53120.13 Ass
34、ertion system functions 53320.14 Coverage system functions 53420.15 Probabilistic distribution functions 53420.16 Stochastic analysis tasks and functions 53620.17 Programmable logic array (PLA) modeling system tasks . 53820.18 Miscellaneous tasks and functions. 54221. I/O system tasks and system fun
35、ctions 54321.1 General. 54321.2 Display system tasks 54321.3 File input-output system tasks and system functions. 55421.4 Loading memory array data from a file . 56521.5 Writing memory array data to a file. 56821.6 Command line input. 56921.7 Value change dump (VCD) files 57222. Compiler directives
36、59322.1 General. 59322.2 Overview . 59322.3 resetall. 59322.4 include 59422.5 define, undef and undefineall 59422.6 ifdef, else, elsif, endif, ifndef 60022.7 timescale . 60322.8 default_nettype . 60422.9 unconnected_drive and nounconnected_drive 60522.10 celldefine and endcelldefine 60522.11 pragma
37、60522.12 line 60622.13 _FILE_ and _LINE_ 60722.14 begin_keywords, end_keywords . 608Part Two: Hierarchy Constructs23. Modules and hierarchy. 61423.1 General. 61423.2 Module definitions. 61423.3 Module instances (hierarchy). 62623.4 Nested modules 63623.5 Extern modules 63723.6 Hierarchical names. 63
38、823.7 Member selects and hierarchical names 64123.8 Upwards name referencing 64223.9 Scope rules 64423.10 Overriding module parameters 64623.11 Binding auxiliary code to scopes or instances . 65424. Programs 65924.1 General. 65924.2 Overview 659BS IEC 62530:2011- vii - IEC 62530:2011(E)IEEE Std 1800
39、-2009Published by IEC under license from IEEE. 2009 IEEE. All rights reserved.24.3 The program construct . 65924.4 Eliminating testbench races . 66324.5 Blocking tasks in cycle/event mode. 66324.6 Programwide space and anonymous programs 66424.7 Program control tasks 66425. Interfaces 66525.1 Genera
40、l. 66525.2 Overview 66525.3 Interface syntax 66625.4 Ports in interfaces. 67025.5 Modports 67125.6 Interfaces and specify blocks. 67725.7 Tasks and functions in interfaces. 67825.8 Parameterized interfaces 68425.9 Virtual interfaces 68625.10 Access to interface objects. 69126. Packages. 69326.1 Gene
41、ral. 69326.2 Package declarations 69326.3 Referencing data in packages. 69426.4 Using packages in module headers 69826.5 Search order rules 69926.6 Exporting imported names from packages 70126.7 The std built-in package. 70227. Generate constructs 70527.1 General. 70527.2 Overview 70527.3 Generate c
42、onstruct syntax 70527.4 Loop generate constructs . 70727.5 Conditional generate constructs. 71127.6 External names for unnamed generate blocks . 71428. Gate-level and switch-level modeling . 71728.1 General. 71728.2 Overview 71728.3 Gate and switch declaration syntax 71728.4 and, nand, nor, or, xor,
43、 and xnor gates. 72328.5 buf and not gates 72428.6 bufif1, bufif0, notif1, and notif0 gates. 72528.7 MOS switches 72628.8 Bidirectional pass switches 72728.9 CMOS switches . 72828.10 pullup and pulldown sources . 72928.11 Logic strength modeling 72928.12 Strengths and values of combined signals . 73
44、128.13 Strength reduction by nonresistive devices 74428.14 Strength reduction by resistive devices 74428.15 Strengths of net types. 74428.16 Gate and net delays 74529. User defined primitives (UDPs). 74929.1 General. 74929.2 Overview 74929.3 UDP definition. 74929.4 Combinational UDPs . 753BS IEC 625
45、30:2011IEC 62530:2011(E) - viii - IEEE Std 1800-2009Published by IEC under license from IEEE. 2009 IEEE. All rights reserved.29.5 Level-sensitive sequential UDPs . 75429.6 Edge-sensitive sequential UDPs 75429.7 Sequential UDP initialization 75529.8 UDP instances 75729.9 Mixing level-sensitive and ed
46、ge-sensitive descriptions. 75829.10 Level-sensitive dominance. 75930. Specify blocks 76130.1 General. 76130.2 Overview 76130.3 Specify block declaration. 76130.4 Module path declarations. 76230.5 Assigning delays to module paths 77130.6 Mixing module path delays and distributed delays 77530.7 Detail
47、ed control of pulse filtering behavior. 77631. Timing checks 78531.1 General. 78531.2 Overview 78531.3 Timing checks using a stability window 78831.4 Timing checks for clock and control signals . 79531.5 Edge-control specifiers 80431.6 Notifiers: user-defined responses to timing violations 80531.7 E
48、nabling timing checks with conditioned events. 80731.8 Vector signals in timing checks . 80831.9 Negative timing checks 80932. Backannotation using the standard delay format (SDF) 81532.1 General. 81532.2 Overview 81532.3 The SDF annotator. 81532.4 Mapping of SDF constructs to SystemVerilog 81532.5
49、Multiple annotations 82032.6 Multiple SDF files . 82132.7 Pulse limit annotation 82132.8 SDF to SystemVerilog delay value mapping. 82232.9 Loading timing data from an SDF file. 82233. Configuring the contents of a design . 82533.1 General. 82533.2 Overview 82533.3 Libraries . 82633.4 Configurations 82833.5 Using libraries and configs 83433.6 Configuration examples. 83533.7 Displaying library binding information . 83733.8 Library mapping examples 83734. Protected envelopes . 84134.1 General. 84134.2 Overview 84134.3 Proc
