1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 09-02-25 Charles F. Saffle Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV A A A A A A A A A A A A REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PR
2、EPARED BY Thanh V. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Thanh V. Nguyen APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 36-BIT REGISTERED BUS TRANSCEIVER WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON SIZE A
3、 CODE IDENT. NO. 16236 DWG NO. V62/03621 YY-MM-DD 03-02-06 REV A PAGE 1 OF 12 AMSC N/A 5962-V042-09 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03621 REV A PA
4、GE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 36-bit registered bus transceiver with three-state outputs microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN i
5、s the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03621 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type G
6、eneric Circuit function 01 74ABTH32543-EP 36-bit registered bus transceiver with three-state outputs 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 100 MS-026 Plastic quad flatpack 1.2.3 Lead finishes. The lead finishes ar
7、e as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-D
8、EFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03621 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 7.0 V Input voltage range (VI) (except I/O ports) . -0.5 V to 7.0 V 2/ Voltage range applied to any output in the high or p
9、ower-off state (VO) . -0.5 V to 5.5 V Current into any output in the low state (IO) 96 mA Input clamp current (IIK) (VI 0 V) . -18 mA Output clamp current (IOK) (VO 0) -50 mA Storage temperature range (TSTG). -65C to 150C Package thermal impedance (JA): 3/ X package . 30C/W 1.4 Recommended operating
10、 conditions. 4/ 5/ Supply voltage range (VCC) . 4.5 V to 5.5 V Input voltage range (VI). 0.0 V to VCC Minimum high level input voltage (VIH) . 2.0 V Maximum low level input voltage (VIL) 0.8 V Maximum input transition rise or fall time (t/v) (Outputs enabled) 10 ns/V Minimum power-up ramp rate (t/VC
11、C) . 200 s/V Operating free-air temperature range (TA). -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicate
12、d under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3/ The package the
13、rmal impedance is calculated in accordance with JESD 51-7. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ Unused con
14、trol pins must be held high or low to prevent them from floating. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03621 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC
15、PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or
16、 online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The
17、 unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, c
18、onstruction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The
19、 logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking p
20、ermitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03621 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Conditions VCC Temperature, TA Device type Min Max Unit Input claim voltage VIKII= -1
21、8 mA 4.5 V 25C, -55C to 125C All -1.2 V IOH= -3 mA 4.5 V 2.5 IOH= -3 mA 5.0 V 3 High level output voltage VOHIOH= -24 mA 4.5 V 25C, -55C to 125C All 2 V Low level output voltage VOLIOL= 48 mA 4.5 V 25C, -55C to 125C All 0.55 V Hysteresis (VT+- VT-) Vhys5.0 V 25C All 100 typical mV Control inputs 1 I
22、nput current IIVI= VCCor GND A or B ports 25C, -55C to 125C All 20 A Three-state power-up current IOZPU2/ VO= 0.5 V to 2.7 V OE = X 0 V to 2.1 V 25C, -55C to 125C All 50 A Three-state power-down current IOZPD2/ VO= 0.5 V to 2.7 V OE = X 2.1 V to 0 V 25C, -55C to 125C All 50 A High state leakage curr
23、ent ICEXVO= 5.5 V, Outputs high 5.5 V 25C, -55C to 125C All 50 A Output current IO3/ VO= 2.5 V 5.5 V 25C, -55C to 125C All -50 -180 mA Outputs high 3 Outputs low 20 Quiescent supply current ICCVI= VCCor GND IO= 0 A Output disabled 5.5 V 25C, -55C to 125C All 2 mA Quiescent supply current delta, TTL
24、input level ICC 4/ One input at 3.4 V, other inputs at VCCor GND 5.5 V 25C, -55C to 125C All 1 mA Input capacitance CIVI= 2.5 V or 0.5 V Control inputs 5.0 V 25C All 3.5 typical pF I/O capacitance CIOVO= 2.5 V or 0.5 V A or B ports 5.0 V 25C All 9.5 typical pF See footnotes ant end of table. Provide
25、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03621 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Conditions VCC Tempe
26、rature, TA Device type Min Max Unit Pulse duration, LEAB or LEBA low tWSee figure 5 4.5 V to 5.5 V 25C, -55C to 125C All 3.3 ns Data before LEAB or LEBA 2.6 Setup time tsuSee figure 5 Data before CEAB or CEBA 4.5 V to 5.5 V 25C, -55C to 125C All 2 ns Data after LEAB or LEBA 1.1 Hold time thSee figur
27、e 5 Data after CEAB or CEBA 4.5 V to 5.5 V 25C, -55C to 125C All 1.2 ns tPLH10.5 6.3 Propagation delay time, A to B or B to A tPHL14.5 V to 5.5 V 25C, -55C to 125C All 0.5 5.9 ns tPLH20.8 7.9 Propagation delay time, LE to A or B tPHL24.5 V to 5.5 V 25C, -55C to 125C All 0.8 6.9 ns tPZH10.8 8.3 Propa
28、gation delay time, output enable, CE to A or B tPZL14.5 V to 5.5 V 25C, -55C to 125C All 1 8.8 ns tPHZ10.5 7.4 Propagation delay time, output disable, CE to A or B tPLZ14.5 V to 5.5 V 25C, -55C to 125C All 1 7.9 ns tPZH20.5 7.6 Propagation delay time, output enable, OE to A or B tPZL24.5 V to 5.5 V
29、25C, -55C to 125C All 1 8.2 ns tPHZ20.5 6.7 Propagation delay time, output disable, OE to A or B tPLZ2CL= 50 pF See figure 5 4.5 V to 5.5 V 25C, -55C to 125C All 0.8 7.2 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
30、specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This parameter is specified by ch
31、aracterization. 3/ No more than one output should be tested at a time, and the duration of the test should not exceed one second. 4/ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCCor GND. Provided by IHSNot for ResaleNo reproduction or
32、 networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03621 REV A PAGE 7 Case X Dimensions Millimeters Millimeters Symbol Min Max Symbol Min Max A 1.60 D/E 15.80 16.20 A1 1.35 1.45 D1/E1 13.80 14.20 A2 0.25 D2/E2 12.
33、00 TYP A3 0.05 e 0.50 BSC b 0.17 0.27 L 0.45 0.75 c 0.13 NOM NOTES: 1. All linear dimensions are in millimeters. 2. This case outline is subject to change without notice. 3. Fall within JEDEC MS-026. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without
34、 license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03621 REV A PAGE 8 Each 18-bit section 1/ Inputs Output CEAB LEAB OEAB A B H X X X Z X X H X ZL H L X Bo2/ L L L L L L L L H H H = High voltage level L = Low voltage level X = Dont care Z = H
35、igh impedance 1/ A-to-B data flow is shown, B-to-A flow control is the same, except that it uses CEBA , LEBA , and OEBA . 2/ Output level before the indicated steady-state input conditions were established. FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted w
36、ithout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03621 REV A PAGE 9 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, O
37、HIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03621 REV A PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 1A9 26 2A11 51 2B10 76 1B8 2 1A10 27 2A12 52 2B9 77 1B7 3 GND 28 2A13 53 GND
38、 78 1B6 4 1A11 29 GND 54 2B8 79 GND 5 1A12 30 2A14 55 2B7 80 1B5 6 1A13 31 2A15 56 2B6 81 1B4 7 1A14 32 2A16 57 2B5 82 1B3 8 GND 33 2A17 58 GND 83 1B2 9 1A15 34 2A18 59 2B4 84 1B1 10 1A16 35 2 CEBA 60 2B3 85 1 CEAB 11 1A17 36 2 OEBA 61 2B2 86 1 OEAB 12 1A18 37 2 LEBA 62 2B1 87 1 LEAB 13 VCC38 VCC63
39、VCC88 VCC14 2A1 39 2 LEAB 64 1B18 89 1 LEBA 15 2A2 40 2 OEAB 65 1B17 90 1 OEBA 16 2A3 41 2 CEAB 66 1B16 91 1 CEBA 17 2A4 42 2B18 67 1B15 92 1A1 18 GND 43 2B17 68 GND 93 1A2 19 2A5 44 2B16 69 1B14 94 1A3 20 2A6 45 2B15 70 1B13 95 1A4 21 2A7 46 2B14 71 1B12 96 1A5 22 2A8 47 GND 72 1B11 97 GND 23 GND 4
40、8 2B13 73 GND 98 1A6 24 2A9 49 2B12 74 1B10 99 1A7 25 2A10 50 2B11 75 1B9 100 1A8 FIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/0
41、3621 REV A PAGE 11 NOTES: 1. CLincludes probe and test-fixture capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when di
42、sabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50 , tr 2.5 ns, tf 2.5 ns. 4. The outputs are measured one at a time with one input transition per measurement. FIGURE 5. Test circuits and timing waveforms. Provided by
43、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03621 REV A PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all insp
44、ection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation,
45、 packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The dat
46、a contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested sourc
47、e(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/03621-01XE 01295 SN74ABTH32543MPZEP 74ABTH32
48、543MEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 Sout
