1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 09-11-09 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV A A A A A A A A A A PAGE 18 19 20 21 22 23 24 25 26 27 REV STATUS OF PAGES REV A A A A A A A A A A
2、A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, 3.3 V CMOS FIRST-IN, FIRST-OUT MEMORIES, MONOLITHIC SILICO
3、N 03-11-06 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03639 REV A PAGE 1 OF 27 AMSC N/A 5962-V005-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236
4、DWG NO. V62/03639 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a 3.3 V CMOS first-in, first-out memories, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identific
5、ation. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03639 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device Memory organization Generic
6、number Circuit function 01 8192 x 18/ 16384 x 9 SN74V263 3.3 V CMOS first-in, first-out memories 02 16384 x 18/ 32768 x 9 SN74V273 3.3 V CMOS first-in, first-out memories 03 32768 x 18/ 65536 x 9 SN74V283 3.3 V CMOS first-in, first-out memories 04 65536 x 18/131072 x 9 SN74V293 3.3 V CMOS first-in,
7、first-out memories 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 80 JEDEC MS-026 Plastic quad flatpack 1.2.3 Lead finishes. The lead finishes areas specified below or other lead finishes as provided by the device manufact
8、urer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 2/ Terminal voltage range with respect to GND, (VTERM) -0.5 V to + 4.5 V Continuous output current, (IO) (VO= 0 to VCC) . 50 mA Storage temperature
9、 range, (TSTG) -55C to +125C 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to these devices. 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and function
10、al operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Provided by IHSNot for ResaleNo reproduction or networking per
11、mitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 3 1.4 Recommended operating conditions. 3/ 4/ Supply voltage, (VCC) . +3.15 V to +3.45 V 5/ Supply voltage, (GND) . 0.0 V High level input voltage, (VIH) +2.0 V
12、 to 5.5 V 6/ Low level input voltage, (VIL) +0.8 V maximum Operating case temperature, (TC) -55C to +125C 7/ 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson
13、 Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identifica
14、tion (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3,
15、 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connection
16、s shall be as specified on figure 2. 3.5.3 Block diagram. The block diagram shall be as specified on figure 3. 3.5.4 Load circuit. The load circuit shall be as specified on figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as specified on figure 5-21. 3/ Long term high temperature stor
17、age and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See manufacturer information for additional information on enhanced plastic packaging. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at th
18、e users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ VCC= 3.3 V 0.15 V, JESD8-A compliant. 6/ Outputs are not 5-V tolerant. 7/ For derating information, please refer to manufacturer information. Provided by IHSNot for
19、 ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions -55C TC +125C 3.15 V VCC 3.45 V unless
20、 otherwise specified Limits Unit Min Max High level output voltage VOHIOH= -2 mA 2.4 V Low level output voltage VOLIOL= 8 mA 0.4 V Input voltage IIVI= 0.4 V to VCC1 A Off state output current IOZOE VIH, VO = 0.4 V to VCC 10 A Supply current ICC1x9 input to x9 output 2/ 3/ 4/ 30 mA Supply current ICC
21、2X18 input to x18 output 2/ 3/ 4/ 35 mA Supply current ICC3Stand by, 2/ 5/ 15 mA Input capacitance CINVI= 0, TC= +25C, f = 1 MHz 10 pF Output capacitance COUTVO= 0, TC= +25C, f = 1 MHz Output deselected ( OE VIH) 10 pF Clock cycle frequency fCLOCKSee figure 5 to 21 6/ 133 MHz Data access time tA2 5
22、ns Clock cycle time tCLK7.5 ns Clock high time tCLKH3.5 ns Clock low time tCLKL3.5 ns Data setup time tDS2.5 ns Data hold time tDH0.5 ns Enable set up time tENS2.5 ns Enable hold time tENH0.5 ns Load set up time tLDS3.5 ns Load hold time tLDH0.5 ns Reset pulse duration 7/ tRS10 ns Reset setup time t
23、RSS15 ns Reset recovery time tRSR10 ns Reset to flag and output time tRSF15 ns Retransmit setup time tRTS3.5 ns Output enable to output in low impedance tOLZ0 ns Output enable to output valid tOE2 6 ns Output enable to output in high impedance tOHZ2 6 ns Write clock to FF or IR tWFF5 ns Read clock t
24、o EF or OR tREF5 ns Clock to asynchronous programmable almost full flag tPAFA12.5 ns Write clock to synchronous programmable almost full flag tPAFS5 ns Clock to asynchronous programmable almost empty flag tPAEA12.5 ns Provided by IHSNot for ResaleNo reproduction or networking permitted without licen
25、se from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 5 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions -55C TC +125C 3.15 V VCC 3.45 V unless otherwise specified Limits Unit Min Max Read cl
26、ock to synchronous programmable almost empty flag tPAESSee figure 5 to 21 6/ 5 ns Clock to half full flag tHF12.5 ns Skew time between read clock and write clock for OR/EF and IR/FF tsk15 ns Skew time between read clock and write clock for PAE and PAF tsk27 ns 1/ Testing and other quality control te
27、chniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product perfor
28、mance is assured by characterization and/or design. 2/ For derating information, please refer to manufacturer information. 3/ Tested with outputs open (IOUT= 0) 4/ RCLK and WCLK switch at 20 MHz and data inputs switch at 10 MHz. 5/ For x18 bus widths, typical ICC2= 5 + fS+0.02 x CLx fS(in mA); for x
29、9 bus widths, typical ICC1= 5 + 0.775 fS+ 0.02 x CLx fS(in mA). These equations are valid under the following conditions: VCC= 3.3 V, TC= 25C, fS= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL= capacitive load (in pF). 6/ All AC timings apply to both FWFT mod
30、e and standard modes. 7/ Pulse durations less than minimum values are not allowed. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 6 Case X Dimens
31、ions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.60 D/E 15.80 16.20 A1 1.35 1.45 D1/E1 13.80 14.20 A2 0.25 TYP D2 12.0 TYP A3 0.05 e 0.65 TYP b 0.22 0.38 K 0.45 0.75 c 0.13 NOM Notes: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. F
32、alls within JEDEC MS-026. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 7 Terminal number Terminal name Terminal number
33、Terminal name Terminal number Terminal name Terminal number Terminal name 1 WEN 21 D7 41 Q7 61 REN 2 SEN 22 D6 42 Q8 62 RCLK 3 DNC 23 GND 43 Q9 63 RM 4 VCC24 D5 44 VCC64 OR/EF 5 DNC 25 D4 45 Q10 65 PFM 6 IW 26 D3 46 GND 66 PAE 7 GND 27 D2 47 Q11 67 VCC8 D17 28 D1 48 GND 68 IP 9 VCC29 D0 49 Q12 69 BE
34、 10 D16 30 GND 50 Q13 70 FSEL1 11 D15 31 Q0 51 VCC71 HF 12 D14 32 Q1 52 Q14 72 FSEL0 13 D13 33 GND 53 Q15 73 OW 14 GND 34 Q2 54 GND 74 PAF 15 D12 35 Q3 55 GND 75 IR/FF 16 D11 36 VCC56 Q16 76 FWFFT/SI 17 D10 37 Q4 57 Q17 77 LD 18 D9 38 Q5 58 VCC78 MRS 19 D8 39 GND 59 OE 79 PRS 20 VCC40 Q6 60 RT 80 WC
35、LK FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 8 FIGURE 3. Block diagram. Provided by IHSNot for ResaleNo repr
36、oduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 9 AC test conditions Input pulse levels GND to 3.0 V Input Rise/Fall time 3 ns 1/ Input timing reference levels 1.5 V Output reference
37、 levels 1.5 V Output load See A and B above Notes: 1. For 133 MHz operation, input rise/fall times are 1.5 ns. 2. Includes probe and jig capacitance. FIGURE 4. Load circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUM
38、BUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 10 FIGURE 5. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 RE
39、V A PAGE 11 FIGURE 6. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 12 Notes: 1. tsk1is the minimum time between a rising RCLK
40、 edge and a rising WCLK edge to ensure that FF goes high (after one WCLK cycle + tWFF). If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tsk1, the FF deassertion can be delayed one additional WCLK cycle. 2. LD = high, EF = high. FIGURE 7. Timing waveforms.
41、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 13 Notes: 1. tsk1is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure
42、that EF goes high (after one RCLK cycle + tref). If the time between the rising edge of WCLK and the rising edge of the RCLK is less than tsk1, the EF deassertion can be delayed one additional WCLK cycle. 2. LD = high. 3. First data word latency: tsk1 + 1*tRCLK+ tREFFIGURE 8. Timing waveforms. Provi
43、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 14 Notes: 1. tsk1is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that O
44、R goes low after two RCLK cycle + tREF. If the time between the rising edge of WCLK and the rising edge of the RCLK is less than tsk1, the OR deassertion might be delayed one additional RCLK cycle. 2. tsk2is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that PAE goes h
45、igh after one RCLK cycle + tPAES. If the time between the rising edge of WCLK and the rising edge of the RCLK is less than tsk2, PAE deassertion might be delayed one additional RCLK cycle. 3. LD = high., OE = low. 4. n = PAE offset, m = PAF offset, D = maximum FIFO depth. 5. if x18 input or x18 outp
46、ut bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both x9 input and x9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for
47、the SN74V293. 6. First data word latency: tsk1 + 2* tRCLK= tREF. FIGURE 9. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03639 REV A PAGE 15 Notes: 1. tsk1is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that IR goes low after one WCLK cycle + tWFF. If the time between the rising edge of RCLK and the rising edge of the WCLK is less than tsk1, IR deassertion mi
