1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type 02. Update boilerplate. Editorial change throughout. - phn 06-02-22 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-06-04 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND
2、AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing CHECKED
3、 BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, QUADRUPLE 2-INPUT POSITIVE AND GATE, MONOLITHIC SILICON YY-MM-DD 03-09-02 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03660 REV B PAGE 1 OF 9 AMSC N/A 5962-V064-12 .Provided by IHSNot for ResaleNo reproducti
4、on or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03660 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance quadruple 2-input positive AND gate microcircuit
5、, with an operating temperature range of -40C to +105C and of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering do
6、cumentation: V62/03660 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LV08AM-EP Quadruple 2-input positive AND gate 02 SN74LV08AT-EP Quadruple 2-input positive AND gate 1.2.2 Case outl
7、ine. The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MO-153 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Ho
8、t solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI) . -0.5 V to +7.0 V 2/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5
9、 V to +7.0 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current (IIK) (VIVCC) 50 mA Continuous output current (IO) (VO= 0 to VCC) 25 mA Continuous current through VCCor GND . 50 mA Package thermal impedance (JA) . 113C/W 4/ Storage temperature range (TSTG) . -65C to +150C
10、1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
11、 absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ This value is limited to 5.5 V maximum. 4/ The package thermal impedance is calculated in accordance
12、 with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03660 REV B PAGE 3 1.4 Recommended operating conditions. 5/ Supply voltage range (VCC) . 2.0 V to
13、5.5 V Minimum high level input voltage (VIH): VCC= 2.0 V 1.5 V VCC= 2.3 V to 2.7 V . VCCx 0.7 VCC= 3.0 V to 3.6 V . VCCx 0.7 VCC= 4.5 V to 5.5 V . VCCx 0.7 Maximum low level input voltage (VIL): VCC= 2.0 V 0.5 V VCC= 2.3 V to 2.7 V . VCCx 0.3 VCC= 3.0 V to 3.6 V . VCCx 0.3 VCC= 4.5 V to 5.5 V . VCCx
14、 0.3 Input voltage range (VI) . 0.0 V to 5.5 V Output voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH): VCC= 2.0 V -50 A VCC= 2.3 V to 2.7 V . -2 mA VCC= 3.0 V to 3.6 V . -6 mA VCC= 4.5 V to 5.5 V . -12 mA Maximum low level output current (IOL): VCC= 2.0 V 50 A VCC= 2.3 V to
15、2.7 V . 2 mA VCC= 3.0 V to 3.6 V . 6 mA VCC= 4.5 V to 5.5 V . 12 mA Maximum input transition rise or fall rate (t/v): VCC= 2.3 V to 2.7 V . 200 ns/V VCC= 3.0 V to 3.6 V . 100 ns/V VCC= 4.5 V to 5.5 V . 20 ns/V Operating free-air temperature range (TA) Device type 01 -40C to +105C Device type 02 -55C
16、 to +125C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.j
17、edec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr
18、om IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03660 REV B PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code,
19、or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical perfor
20、mance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth
21、 table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as
22、shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03660 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions -4
23、0C TA 105C 2/ -55C TA 125C 3/ unless otherwise specified VCCLimits Unit Min Max High level output voltage VOHIOH= -50 A 2.0 V to 5.5 V VCC 0.1 V IOH= -2 mA 2.3 V 2.0 IOH= -6 mA 3.0 V 2.48 IOH= -12 mA 4.5 V 3.8 Low level output voltage VOHIOL= 50 A 2.0 V to 5.5 V 0.1 V IOL= 2 mA 2.3 V 0.4 IOL= 6 mA 3
24、.0 V 0.44 IOL= 12 mA 4.5 V 0.55 Input current IIVI= 5.5 V or GND 0.0 V to 5.5 V 1.0 A Quiescent supply current ICCVI= VCCor GND, IO= 0 A 5.5 V 20.0 A Input/output power-off leakage current IoffVIor VO= 0.0 V to 5.5 V 0.0 V 5.0 A Input capacitance CIVI= VCCor GND 3.3 V 3.3 TYP pF 5.0 V 3.3 TYP Power
25、dissipation capacitance CpdCL= 50 pF, TA = 25C f = 10 MHz 3.3 V 8 TYP pF 5.0 V 10 TYP Quiet output, maximum dynamic VOLVOL(P) 4/ CL= 50 pF, TA = 25C 3.3 V 0.8 V Quiet output, minimum dynamic VOLVOL(V) 4/ -0.8 Quiet output, minimum dynamic VOHVOH(V) 4/ 3.1 Typ High level dynamic input voltage VIH(D)
26、4/ 2.31 Low level dynamic input voltage VIL(D) 4/ 0.99 Propagation delay time, from A or B to Y tPLH, tPHLCL= 50 pF, TA= 25C See figure 5 3.3 V 0.3 V 12.3 ns 5.0 V 0.5 V 7.9 Propagation delay time, from A or B to Y tPLH, tPHLCL= 50 pF See figure 5 3.3 V 0.3 V 1.0 16.0 5.0 V 0.5 V 1.0 12.0 1/ Testing
27、 and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific param
28、etric testing, product performance is assured by characterization and/or design. 2/ For device type 01 only. 3/ For device type 02 only. 4/ Characteristics are for surface-mount packages only. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE S
29、UPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03660 REV B PAGE 6 Case X SEATINGPLANESEEDETAIL AbD1 7814E E1AA1e0.25(.010)c0-8LDETAIL AGAGEPLANEM0.10(.004)0.10(.004)Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20
30、- .047 E 4.30 4.50 .169 .177 A1 0.05 0.15 .002 .006 E1 6.20 6.60 .244 .260 b 0.19 0.30 .007 .012 e 0.65 NOM .026 NOM c 0.15 NOM .006 NOM L 0.50 0.75 .020 .030 D 4.90 5.10 .193 .201 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion
31、not to exceed 0.15 mm. 3. Falls within JEDEC MO-153. 4. All linear dimensions are shown in millimeters (inches). Inches equivalents are given for general information only. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFEN
32、SE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03660 REV B PAGE 7 (each gate) Inputs Output Y A B H H h L X L X L L X = Immaterial FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal
33、 symbol 1 1A 8 3Y 2 1B 9 3A 3 1Y 10 3B 4 2A 11 4Y 5 2B 12 4A 6 2Y 13 4B 7 GND 14 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62
34、/03660 REV B PAGE 8 Notes: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled
35、by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50, tr 3 ns, tf 3 ns. 4. The outputs are measured one at a time with one input transition per measurement. 5. For 3-state and Open Drain outputs tests: tPLH/tPHLS1 = Open tPLZ/t
36、PZLS1 = VCCtPHZ/tPZHS1 = GND Open Drain S1 = VCCFIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03660 REV B PAGE 9 4.
37、VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labelin
38、g of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electros
39、tatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be mo
40、dified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all curre
41、nt sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top-Side Marking V62/03660-01XE 01295 SN74LV08ATPWREP LV08AEP V62/03660-02XE 01295 SN74LV08AMPWREP LV08AEP 1/ The vendor ite
42、m drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
