1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct vendor part number in 6.3. Updated boiler plate. - phn 04-06-16 Thomas M. Hess B Add vendor part number for device type 02 in 6.3 - phn 04-10-06 Thomas M. Hess C Correct number of pins in case outline 1.2.2 - phn 05-07-21 Thomas M. Hess D Update boi
2、lerplate. Correct lead finishes - CFS 05-11-08 Thomas M. Hess E Add device type 04-06. - PHN 06-10-02 Thomas M. Hess F Update boilerplate paragraphs to current requirements. - PHN 12-07-23 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OH
3、IO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 REV PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PR
4、EPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON YY MM DD 04-04-19 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO.
5、V62/04609 REV E PAGE 1 OF 59 AMSC N/A 5962-V084-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04609 REV F PAGE 2 1. SCOPE 1.1 Scope. This drawing documents th
6、e general requirements of a high performance Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an adm
7、inistrative control number for identifying the item on the engineering documentation: V62/04609 - 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Circuit function 01 2/ SM320C6414-EP Fixed Point Digital Signa
8、l Processor 02 2/ SM320C6415-EP Fixed Point Digital Signal Processor 03 2/ SM320C6416-EP Fixed Point Digital Signal Processor 04 SM320C6414-EP Fixed Point Digital Signal Processor 05 SM320C6415-EP Fixed Point Digital Signal Processor 06 SM320C6416-EP Fixed Point Digital Signal Processor 1.2.2 Case o
9、utline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 532 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B T
10、in-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. 2/ Device is no longer available. Provided by IHSNot for ResaleNo reproduction or networking permitted without
11、 license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04609 REV F PAGE 3 1.3 Absolute maximum ratings. 3/ Supply voltage ranges: (CVDD) . -0.3 V to +1.8 V 4/ (DVDD) -0.3 V to +4.0 V 4/ Input voltage ranges: (VI), (except PCI) . -0.3 V to +4.0 V
12、(VIP), (PCI) device type 02, 03, 05, and 06 only . -0.5 V to DVDD+ 0.5 V Output voltage ranges: (VO) (except PCI) -0.3 V to +4.0 V (VOP), (PCI) device type 02, 03, 05, and 06 only -0.5 V to DVDD+ 0.5 V Operating case temperature ranges, (TC): (A version) . -40C to +105C Storage temperature range, (T
13、STG) -65C to +150C 1.4 Recommended operating conditions. Supply voltage, core (CVDD) (-50AEP device) . +1.19 V to +1.31 V 5/ Supply voltage, I/O (DVDD) . +3.14 V to +3.46 V Supply ground, (VSS) 0 V Minimum high level input voltage, (VIH) (except PCI) . +2.0 V Maximum low level input voltage, (VIL) (
14、except PCI) +0.8 V Input voltage, (VIP) (PCI) device type 02, 03, 05, and 06 only -0.5 V to DVDD+ 0.5 V High level input voltage (VIHP) (PCI) device type 02, 03, 05, and 06 only . 0.5DVDDto DVDD+ 0.5 V Low level input voltage, (VILP) (PCI) device type 02, 03, 05, and 06 only . -0.5 V to 0.3DVDDOpera
15、ting case temperature (TC),(A version) . -40C to +105C Thermal resistance Air Flow (m/s) 6/ C/W C/W (with heat sink) 7/ Junction to case, (RJC) N/A 1.55 1.00 Junction to board, (RJB) N/A 9.10 9.00 Junction to free air, (RJA) 0.00 17.90 13.80 Junction to free air, (RJA) 0.5 15.02 8.95 Junction to fre
16、e air, (RJA) 1.0 13.40 7.35 Junction to free air, (RJA) 2.0 11.89 6.46 Junction to package top, (PsiJT) N/A 0.50 0.50 Junction to board, (PsiJB) N/A 7.40 7.40 3/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and
17、functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4/ All voltage values are with respect to VSS. 5/ Futu
18、re variants of the C641x DSPs may operate at voltage ranging from 0.9 V to 1.4 V to provide a range of system power/performance options. Manufacturer highly recommends that users design in a supply that can handle multiple voltages within this range ( i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V with 3
19、% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Example of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends. Not incorporating a flexible supply may limit the systems ability t
20、o easily adapt future versions of C641x devices. 6/ m/s = meters per second. 7/ These thermal resistance numbers were modeled using a heat sink, part number 3740224B00035, manufactured by AAVID Thermalloy. AAVID Thermalloy also manufacturers a similar epoxy mounted heat sink, part number 374024B0000
21、0. Manufacturer recommends a passive, laminar heat sink, similar to the part numbers mentioned above. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04609 REV F P
22、AGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Par
23、ts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part numb
24、er and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, a
25、nd physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure
26、 3. 3.5.4 Timing reference. The timing reference circuit for AC timing measurements shall be as specified in figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figure 5-40. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFE
27、NSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04609 REV F PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test condition -40C TC+105C 1.19 V CVDD 1.31 V 3.14 V DVDD 3.46 V Device type: All unless otherwise noted Limits Unit Min Max High lev
28、el output voltage (except PCI) VOHDVDD= Min, IOH= Max 2.4 V High level output voltage (PCI) VOHPIOHP= -0.5 mA, DVDD= 3.3 V Device type 02, 03, 05, and 06 only 0.9DVDD 2/ Low level output voltage (except PCI) VOLDVDD= Min, IOL= Max 0.4 Low level output voltage (PCI) VOLPIOLP= 1.5 mA, DVDD= 3.3 V Devi
29、ce type 02, 03, 05, and 06 only 0.1DVDD 2/ Input current (except PCI) IIVI= VSSto DVDDno opposing internal resistor 10 A VI= VSSto DVDDopposing internal pullup resistor 3/ 50 150 VI= VSSto DVDDno opposing internal pulldown resistor 3/ -150 -50 Input leakage current (PCI) 4/ IIP0 VIP DVDD= 3.3 V, Dev
30、ice type 02, 03, 05, and 06 only 10 High level output current IOHEMIF, CLKOUT4, CLKOUT6, EMUx -16 mA Timer, UTOPIA, TDO, GPIO (Excluding GP15:9, 2, 1), McBSP -8 PCI/HPI -0.5 2/ Low level output current IOLEMIF, CLKOUT4, CLKOUT6, EMUx 16 Timer, UTOPIA, TDO, GPIO (Excluding GP15:9, 2, 1), McBSP 8 PCI/
31、HPI 1.5 2/ Off state output current IOZVO= DVDDor 0 V 10 A Core supply current 5/ ICDDCVDD= 1.4 V, CPU clock = 720 MHz 900 Typ 6/ mA CVDD= 1.4 V, CPU clock = 600Hz 750 Typ 6/ CVDD= 1.2 V, CPU clock = 500Hz 550 Typ I/O supply current 5/ IDDDCVDD= 3.3 V, CPU clock = 600Hz 125 Typ 6/ Input capacitance
32、CI10 pF Output capacitance CO10 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04609 REV F PAGE 6 TABLE I. Electrical performance chara
33、cteristics - Continued. No. Test Symbol Test condition -40C TC+105C 1.19 V CVDD 1.31 V 3.14 V DVDD 3.46 V Device type: All unless otherwise noted Limits Unit PLL Mode x12 PLL Mode x6 x1 (Bypass) Min Max Min Max Min Max INPUT AND OUTPUT CLOCKS Timing requirements for CLKIN for 50AEP devices 7/ 8/ 9/
34、1 Cycle time, CLKIN tc(CLKIN)See figure 6 24 33.3 13.3 33.3 13.3 33.3 ns 2 Pulse duration, CLKIN high tw(CLKINH)0.4C 0.4C 0.45C 3 Pulse duration, CLKIN high tw(CLKINL)0.4C 0.4C 0.45C 4 Transition time, CLKIN tt(CLKIN)5 5 1 No. Test Symbol Test condition -40C TC+105C 1.19 V CVDD 1.31 V 3.14 V DVDD 3.
35、46 V Device type: All unless otherwise noted Limits Unit CLKMODE = X1, X6, X12 Min Max INPUT AND OUTPUT CLOCKS (CONTINUED) Switching characteristics for CLKOUT4 10/ 11/ 12/ 1 Cycle to cycle jitter, CLKOUT4 tj(CKO4)See figure 7 0 175 ps 2 Pulse duration, CLKOUT4 high tw(CKO4H)2P-0.7 2P+0.7 ns 3 Pulse
36、 duration, CLKOUT4 low tw(CKO4L)2P-0.7 2P+0.7 4 Transaction time, CLKOUT4 tt(CKO4)1 Switching characteristics for CLKOUT6 10/ 11/ 12/ 1 Cycle to cycle jitter, CLKOUT6 tj(CKO6)See figure 7 0 175 ps 2 Pulse duration, CLKOUT6 high tw(CKO6H)3P-0.7 3P+0.7 ns 3 Pulse duration, CLKOUT6 low tw(CKO6L)3P-0.7
37、3P+0.7 4 Transaction time, CLKOUT6 tt(CKO6)1 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04609 REV F PAGE 7 TABLE I. Electrical perf
38、ormance characteristics - Continued. No. Test Symbol Test condition -40C TC+105C 1.19 V CVDD 1.31 V 3.14 V DVDD 3.46 V Device type: All unless otherwise noted Limits Unit Min Max INPUT AND OUTPUT CLOCKS (CONTINUED) Timing requirements for ECLKIN for EMIFA and EMIFB 7/ 12/ 13/ 1 Cycle time, ECLKIN tc
39、(EKI)See figure 8 6 14/ 16P ns 2 Pulse duration, ECLKIN high tw(EHIH)2.7 3 Pulse duration, ECLKIN low tw(EKIL)2.7 4 Transaction, ECLKIN tt(EKI)2 Switching characteristics for ECLKOUT1 for EMIFA and EMIFB modules 10/ 13/ 15/ 16/ 1 Cycle to cycle jitter, ECLKOUT1 tj(EKO1)See figure 8 0 175 17/ ps 2 Pu
40、lse duration, ECLKOUT1 high tw(EKO1H)EH-0.7 EH+0.7 ns 3 Pulse duration, ECLKOUT1 low tw(EKO1L)EH-0.7 EH+0.7 4 Transition time, ECLKOUT1 tt(EKO1)1 5 Delay time, ECLKIN high to ECLKOUT1 high td(EKIH-EKO1L)1 8 6 Delay time, ECLKIN low to ECLKOUT1 low td(EKIL-EKO1L)1 8 Switching characteristics for ECLK
41、OUT2 for EMIFA and EMIFB modules 10/ 13/ 18/ 1 Cycle to cycle jitter, ECLKOUT2 tj(EKO2)0 175 17/ ps 2 Pulse duration, ECLKOUT2 high tw(EKO2H)0.5NE-0.7 0.5NE+0.7 ns 3 Pulse duration, ECLKOUT2 low tw(EKO2L)0.5NE-0.7 0.5NE+0.7 4 Transition time, ECLKOUT2 tt(EKO2)1 5 Delay time, ECLKIN high to ECLKOUT2
42、high td(EKIH-EKO2L)1 8 6 Delay time, ECLKIN low to ECLKOUT2 low td(EKIL-EKO2L)1 8 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04609
43、REV F PAGE 8 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition -40C TC+105C 1.19 V CVDD 1.31 V 3.14 V DVDD 3.46 V Device type: All unless otherwise noted Limits Unit Min Max ASYNCHRONOUS MEMORY TIMING Timing requirements for asynchronous memory cycles for EMI
44、FA module 13/ 19/ 20/ 3 Setup time, EDx valid before ARE high tsu(EDV-AREH)See figure 9 and 10 6.5 ns 4 Hold time, EDx valid after ARE high th(AREH-EDV)1 6 Setup time, ARDY valid before ECLKOUT1 high tsu(ARDY-EKO1H)3 7 Hold time, ARDY valid after ECLKOUT1 high th(EKO1H-ARDY)1.5 Switching characteris
45、tics for asynchronous memory cycles for EMIFA module 13/ 20/ 21/ 22/ 1 Output setup time, select signals valid to ARE low tosu(SELV-AREL)See figure 9 and 10 RS*E-1.5 ns 2 Output hold time, ARE high to select signals invalid toh(AREH-SELIV)RH*E-1.9 5 Delay time, ECLKOUT1 high to ARE valid td(EKO1H-AR
46、EV)1 7 8 Output setup time, select signals valid to AWE low tosu(SELV-AWEL)WS*E-1.7 9 Output hold time, AWE high to select signals invalid toh(AWEH-SELIV)WH*E-1.8 10 Delay time, ECLKOUT1 high to AWE valid td(EKO1H-AWEV)1.3 7.1 Timing requirements for asynchronous memory cycles for EMIFB module 13/ 1
47、9/ 20/ 3 Setup time, EDx valid before ARE high tsu(EDV-AREH)See figure 9 and 10 6.2 ns 4 Hold time, EDx valid after ARE high th(AREH-EDV)1 6 Setup time, ARDY valid before ECLKOUT1 high tsu(ARDY-EKO1H)3 7 Hold time, ARDY valid after ECLKOUT1 high th(EKO1H-ARDY)1.7 Switching characteristics for asynch
48、ronous memory cycles for EMIFB module 13/ 20/ 21/ 22/ 1 Output setup time, select signals valid to ARE low tosu(SELV-AREL)See figure 9 and 10 RS*E-1.6 ns 2 Output hold time, ARE high to select signals invalid toh(AREH-SELIV)RH*E-1.7 5 Delay time, ECLKOUT1 high to ARE valid td(EKO1H-AREV)0.8 6.6 8 Output setup time, select signals valid to AWE low tosu
