1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 11-07-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV
2、PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.3-
3、V ABT 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-05-04 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04717 REV A PAGE 1 OF 14 AMSC N/A 5962-V060-11 .Provided by IHSNot for ResaleNo reproduction or networking permitted without licens
4、e from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT 16-bit bus transceiver and register with 3-state outputs microcircuit, with an
5、operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04717 - 01 X E
6、Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVTH16652-EP 3.3-V ABT 16-bit bus transceiver and register with 3-state outputs 1.2.2 Case outline. The case outline is as specified herein. Outli
7、ne letter Number of pins JEDEC PUB 95 Package style X 56 MO-153 Plastic small-outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold
8、flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to
9、4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high (VO) -0.5 V to VCC+ 0.5 V 2/ Current into any output in the low state (IO) . 128 mA Current into any
10、output in the high state (IO) . 64 mA 3/ Input clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Package thermal impedance (JA) . 81C/W 4/ Storage temperature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ Supply voltage (VCC) . 2.7 V to 3.6 V Minimum
11、 high level input voltage (VIH) 2 V Maximum low level input voltage (VIL) . 0.8 V Maximum input voltage (VI) . 5.5 V Maximum high level output current (IOH) . -32 mA Maximum low level output current (IOL) . 64 mA Maximum input transition rise or fall rate (t/v) (Outputs enabled) 10 ns/V Minimum powe
12、r-up ramp rate (t/VCC) 200 s/V Operating free-air temperature range (TA) -40C to +85C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Lea
13、ded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to
14、 the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The
15、 input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3/ This current flows only when the output is in the high state and VO VCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ All unused control inputs
16、 of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 REV A PAGE 4 3. REQUIREMENTS 3.1
17、Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacture
18、rs part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, con
19、struction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Function table. The function table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4
20、Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY
21、 CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Input clamp voltage VIKII= -18 mA 2.7 V 25C, -40C to 85C All -1.2 V High level outp
22、ut voltage VOHIOH= -100 A 2.7 V to 3.6 V VCC 0.2 V IOH= -8 mA 2.7 V 2.4 IOH= -32 mA 3 V 2 Low level output voltage VOLIOL= 100 A 2.7 V 0.2 V IOL= 24 mA 0.5 IOL= 16 mA 3 V 0.4 IOL= 32 mA 0.5 IOL= 64 mA 0.55 Input current IIControl inputs. VI= VCCor GND 3.6 V 1 A Control inputs., VI= 5.5 V 0 V or 3.6
23、V 10 A or B ports, VI= 5.5 V 2/ 3.6 V 20 A or B ports, VI= VCC2/ 1 A or B ports, VI= 0 V 2 -5 Input/output power-off leakage current IoffVIor VO= 0 V to 4.5 V 0 V 100 A Input current (hold) II(hold)A or B ports, VI= 0.8 V 3 V 75 AA or B ports, VI= 2 V -75 A or B ports. VI= 0 V to 3.6 V 3/ 3.6 V 500
24、3-state output current power-up IOZPUVO= 0.5 V to 3 V OE = dont care 0 V to 1.5 V 100 A 3-state output current power-down IOZPDVO= 0.5 V to 3 V OE = dont care 1.5 V to 0 V 100 A Quiescent supply current ICCOutputs high. VI= VCCor GND, IO= 0 A 3.6 V 0.19 mA Outputs low. VI= VCCor GND, IO= 0 A 5 Outpu
25、ts disabled. VI= VCCor GND, IO= 0 A 0.19 Quiescent supply current delta ICC4/ One input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 3.6 V 0.2 mA Input capacitance CiVI= 3 V or 0 V 3.3 V 25C 4 TYP pF Input/output capacitance CioVO= 3 V or 0 V 10 TYP pF See footnotes at end of table. Provided by IH
26、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevic
27、e type Limits Unit Min Max Clock frequency fclock2.7 V 25C, -40C to 85C All 150 MHz 3.3 V 0.3 V 150 Pulse duration, CLK high or low twSee figure 5. 2.7 V 3.3 ns 3.3 V 0.3 V 3.3 Setup time, A or B before CLKAB or CLKBA, data high tsu2.7 V 1.5ns 3.3 V 0.3 V 1.2 Setup time, A or B before CLKAB or CLKBA
28、, data low 2.7 V 2.8 ns 3.3 V 0.3 V 2 Hold time, A or B after CLKAB or CLKBA, data high th2.7 V 0 ns 3.3 V 0.3 V 0.5 Hold time, A or B after CLKAB or CLKBA, data low 2.7 V 0.5 ns 3.3 V 0.3 V 0.5 Maximum frequency fmaxCL= 50 pF 2.7 V 150 MHz 3.3 V 0.3 V 150 Propagation delay time, CLK to B or A tPLHC
29、L= 50 pF See figure 5. 2.7 V 4.7 ns 3.3 V 0.3 V 1.3 4.2 tPHL2.7 V 4.73.3 V 0.3 V 1.3 4.2 Propagation delay time, A or B to B or A tPLH2.7 V 3.93.3 V 0.3 V 1 3.4 tPHL2.7 V 3.93.3 V 0.3 V 1 3.4 Propagation delay time, SAB or SBA to B or A tPLH2.7 V 5.43.3 V 0.3 V 1 4.5 tPHL2.7 V 5.43.3 V 0.3 V 1 4.5 P
30、ropagation delay time, output enable, OEBA or to A tPZH2.7 V 5.23.3 V 0.3 V 1 4.3 tPZL2.7 V 5.23.3 V 0.3 V 1 4.3 Propagation delay time, output enable, OEAB to B tPZH2.7 V 4.93.3 V 0.3 V 1.3 4.2 tPZL2.7 V 4.93.3 V 0.3 V 1.3 4.2 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduct
31、ion or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 REV A PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max
32、Propagation delay time, output disable, OEBA to A tPHZCL= 50 pF See figure 5. 2.7 V 25C, -40C to 85C All 6.1 ns 3.3 V 0.3 V 2 5.6 tPLZ2.7 V 6.13.3 V 0.3 V 2 5.4 Propagation delay time, output disable, OEAB to B tPHZ2.7 V 6.2ns 3.3 V 0.3 V 1.3 5.5 tPLZ2.7 V 6.23.3 V 0.3 V 1.3 5.5 1/ Testing and other
33、 quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric test
34、ing, product performance is assured by characterization and/or design. 2/ Unused pins at VCCor GND. 3/ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. 4/ This is the increase in supply current for each input th
35、at is at the specified TTL voltage level, rather than VCCor GND. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 REV A PAGE 8 Case X Dimensions Symbol Millim
36、eters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - 0.047 E 6.00 6.20 0.236 0.244 A1 0.25 TYP 0.010 TYP E1 7.90 8.30 0.311 0.327 b 0.17 0.27 0.007 0.011 e 0.50 BSC 0.020 BSC c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 13.90 14.10 0.547 0.555 Q 0.05 0.15 0.002 0.006 N
37、OTES: 1. All linear dimensions are in millimeters (inches). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 millimeters (0.006 in). 4. Fall within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for Res
38、aleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 REV A PAGE 9 Function Table Inputs Data I/O 1/ Operation or Function OEAB OEBA CLKAB CLKBA SAB SBA A1 A8 B1 B8 L L H H H or L H or L X
39、X X X Input Input Input Input Isolation Store A and B data X H H H H or L X X 2/ X X Input Input Unspecified 2/ Output Store A, hold B Store A in both registers L L X L H or L X X X X 2/ Unspecified 2/ Output Input Input Hold A, store B Store B in both registers L L L L X X X H or L X X L H Output O
40、utput Input Input Real-time B data to A bus Stored B data to A bus H H H H X H or L X X L H X X Input Input Output Output Real-time A data to B bus Stored A data to B bus H L H or L H or L H H Output Output Stored A data to B bus and stored B data to A bus H = High voltage level L = Low voltage leve
41、l X = Immaterial = Low-to-high transition 1/ The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. 2/ Select cont
42、rol = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers. FIGURE 2. Function table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT
43、NO. 16236 DWG NO. V62/04717 REV A PAGE 10 OEAB OEBA CLKAB CLKBA SAB SBA OEAB OEBA CLKAB CLKBA SAB SBA L L X X X L H H X X L X REAL-TIME TRANSFER REAL-TIME TRANSFER BUS B TO BUS A BUS A TO BUS B OEAB OEBA CLKAB CLKBA SAB SBA OEAB OEBA CLKAB CLKBA SAB SBA X L L H X H X X X X X X X X H L H or L H or L
44、H H STORAGE FROM TRANSFER STORED DATA A, B, OR A AND B TO A AND/OR B FIGURE 2. Function table - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 RE
45、V A PAGE 11 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 REV A PAGE 12 Device type 01 Case outline X Terminal number Terminal sym
46、bol Terminal number Terminal symbol 1 1OEAB 29 2OEBA 2 1CLKAB 30 2CLKBA 3 1SAB 31 2SBA4 GND 32 GND 5 1A1 33 2B8 6 1A2 34 2B77 VCC35 VCC8 1A3 36 2B69 1A4 37 2B5 10 1A5 38 2B411 GND 39 GND 12 1A6 40 2B3 13 1A7 41 2B214 1A8 42 2B1 15 2A1 43 1B816 2A2 44 1B7 17 2A3 45 1B618 GND 46 GND 19 2A4 47 1B5 20 2
47、A5 48 1B421 2A6 49 1B3 22 VCC50 VCC23 2A7 51 1B224 2A8 52 1B1 25 GND 53 GND 26 2SAB 54 1SBA 27 2CLKAB 55 1CLKBA28 2OEAB 56 1OEBA FIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04717 REV A PAGE 13 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output con
