1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - ro 12-10-23 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE
2、 REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, DIGITAL-LINEAR, 4.5 V to
3、20 V INPUT, 3 A OUTPUT SYNCHRONOUS PULSE WIDTH MODULATOR, MONOLITHIC SILICON 06-01-20 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06610 REV A PAGE 1 OF 16 AMSC N/A 5962-V015-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-D
4、EFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06610 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 4.5 V to 20 V input, 3 A output synchronous pulse width modulator microcircuit, with an operating tempera
5、ture range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06610 - 01 X E Drawing Device t
6、ype Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Output voltage Circuit function 01 TPS54350-EP Adjustable to 0.891 V 4.5 V to 20 V input, 3 A output synchronous pulse width modulator 1.2.2 Case outline(s). The case outline(s) are as s
7、pecified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MO-153 Plastic small outline with thermal pad 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-l
8、ead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Input voltage range (VI): VIN pin -0.3 V to 21.5 V VSENSE, UVLO pins . -0.3 V to 8 V SYNC, ENA pins . -0.3 V to 4 V BOOT pin . VI(PH) + 8 V Output voltage range (VO): VBIAS, LSG pins -0.3 V to 8.5 V SY
9、NC, RT, COMP pins -0.3 V to 4 V PWRGD pin -0.3 V to 6 V PH pin -1.5 V to 22 V _ 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond thos
10、e indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COL
11、UMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06610 REV A PAGE 3 1.3 Absolute maximum ratings - continued. 1/ Source current (IO): PH pin Internally limited (A) LSG (steady state current) pin . 10 mA COMP, VBIAS pins 3 mA Sink current (IS): SYNC pin . 5 mA LSG (steady state current) pin . 100
12、mA PH (steady state current) pin 500 mA COMP pins . 3 mA ENA, PWRGD pins 10 mA Voltage differential (AGND to PGND pins) . 0.3 V Continuous power dissipation See power dissipation rating table Operating virtual junction temperature range (TJ) -55C to +150C Storage temperature range (TSTG) -65C to +15
13、0C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds +260C 1.4 Recommended operating conditions. 2/ Input voltage range (VI) 4.5 V to 20 V Operating junction temperature range (TJ) -55C to +125C 1.5. Power dissipation rating table. 3/ Package Thermal impedance junction-to-ambient TA= 25C
14、power rating TA= 70C power rating TA= 85C power rating Case X with solder 4/ 42.1C/W 2.36 W 1.31 W 0.95 W Case X without solder 151.9C/W 0.66 W 0.36 W 0.26 W 2/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distribut
15、or maintain no responsibility or liability for product used beyond the stated limits. 3/ For more information on the case X (PWP) package, see the manufacturers technical brief SLMA002. 4/ Test board conditions: a. Thickness: 0.062 inch. b. 3 inch x 3 inch. c. 2.0 ounce copper traces located on the
16、top and bottom of the printed circuit board (PCB) for soldering. d. Copper areas located on top and bottom of the printed circuit board (PCB) for soldering. e. Power and ground planes, 1 ounce copper (0.036 mm) thick. f. Thermal vias, 0.33 mm diameter, 1.5 mm pitch. g. Thermal isolation of power pla
17、ne. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06610 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 Registered and
18、 Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manuf
19、acturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Elec
20、trical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagr
21、ams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown
22、in figure 4. 3.5.5 Test circuit. The test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06610 REV A PAGE 5 TABLE I. Electr
23、ical performance characteristics. 1/ 2/ Test Symbol ConditionsTemperature, TJDevice type Limits Unit Min Max Supply voltage section Quiescent current I(Q)Operating current, PH pin open, no external low side MOSFET, RT = Hi-Z -55C to +125C 01 5 typical mA Shutdown, ENA = 0 V 1 typical Start threshold
24、 voltage VIN-55C to +125C 01 4.52 V Stop threshold voltage VIN-55C to +125C 01 3.63 Hysteresis VIN-55C to +125C 01 350 typical mV Under voltage lock out (UVLO pin) section Start threshold voltage -55C to +125C 01 1.28 V Stop threshold voltage -55C to +125C 01 1.02 V Hysteresis voltage -55C to +125C
25、01 100 typical mV Bias voltage (VBIAS pin) section Output voltage VBIAS IVBIAS= 1 mA, VIN 12 V -55C to +125C 01 7.5 8.035 V IVBIAS= 1 mA, VIN = 4.5 V -55C to +125C 4.4 4.5 Reference system accuracy section Reference voltage 25C 01 0.888 0.896 V -55C to +125C 0.88 0.899 Oscillator (RT pin) section In
26、ternally set PWM switching frequency RT grounded -55C to +125C 01 183 300 kHz RT open 396 600 Externally set PWM switching frequency RT = 100 k, (1 % resistor to AGND) -55C to +125C 01 400 595 kHz See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted wit
27、hout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06610 REV A PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ 2/ Test Symbol ConditionsTemperature, TJDevice type Limits Unit Min Max Falling edge triggered bidirection
28、al SYNC system (SYNC pin) section SYNC out low to high rise time 10% / 90%, 25 pF to ground 3/ -55C to +125C 01 500 ns SYNC out high to low fall time 90% / 10%, 25 pF to ground 3/ -55C to +125C 01 10 ns Falling edge delay time Delay from rising edge to 3/ rising edge of PH pins, see figure 4 -55C to
29、 +125C 01 180 typical Minimum input pulse width RT = 100 k 3/ -55C to +125C 01 100 typical ns Delay (falling edge SYNC to rising edge PH) RT = 100 k 3/ -55C to +125C 01 360 typical ns SYNC out high level voltage 50 k resistor to ground, no pull up resistor -55C to +125C 01 2.5 V SYNC out low level v
30、oltage -55C to +125C 01 0.6 V SYNC in low level threshold -55C to +125C 01 0.8 V SYNC in high level threshold -55C to +125C 01 2.3 V SYNC in frequency 3/ range Percentage of programmed frequency -55C to +125C 01 -10% 10% 225 770 kHz Feed forward modulation (internal signal) section Modulation gain V
31、IN = 12 V +25C 01 8 typical V/V Modulation gain variation -55C to +125C 01 -25% 25% Minimum controllable ON time 3/ -55C to +125C 01 180 typical ns Maximum duty factor VIN = 4.5 V 3/ -55C to +125C 01 80% See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permit
32、ted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06610 REV A PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ 2/ Test Symbol ConditionsTemperature, TJDevice type Limits Unit Min Max Error amplifier section (VS
33、ENSE and COMP pins) Error amplifier open loop voltage gain 3/ -55C to +125C 01 60 dB Error amplifier unity gain bandwidth 3/ -55C to +125C 01 1 MHz Input bias current, VSENSE pin 3/ -55C to +125C 01 500 nA Output voltage slew rate (symmetric) COMP 3/ -55C to +125C 01 1.5 typical V/s Enable (ENA pin)
34、 section Disable low level input voltage -55C to +125C 01 0.5 V Internal slow start time (10% to 90%) fS= 250 kHz, RT = ground 3/ -55C to +125C 01 4.6 typical ms fS= 500 kHz, RT = Hi - Z 3/ 2.3 typical Pull up current source -55C to +125C 01 1.8 10 A Pull down MOSFET II(ENA) = 1 mA -55C to +125C 01
35、0.1 typical V Power good (PWRGD pin) section Power good threshold Rising voltage -55C to +125C 01 97 % typical Rising edge delay 3/ fS= 250 kHz -55C to +125C 01 4 typical ms fS= 500 kHz 2 typical Output saturation voltage PWRGD ISINK= 1 mA, VIN 4.5 V -55C to +125C 01 0.05 typical V ISINK= 100 A, VIN
36、 = 0 V 0.76 typical Open drain leakage current PWRGD Voltage on PWRGD = 6 V -55C to +125C 01 3 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236
37、 DWG NO. V62/06610 REV A PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ 2/ Test Symbol ConditionsTemperature, TJDevice type Limits Unit Min Max Current limit section Current limit VIN = 12 V +25C 01 3 7.2 A Current limit Hiccup time fS= 500 kHz, 4/ -55C to +125C 01 4.5 typical
38、ms Thermal shutdown section Thermal shutdown trip point 4/ -55C to +125C 01 165 typical C Thermal shutdown hysteresis 4/ -55C to +125C 01 7 typical C Low side MOSFET driver (LSG pin) section Turn on rise time 3/ (10% / 90%) VIN = 4.5 V, capacitive load = 1000 pF -55C to +125C 01 15 typical ns Dead t
39、ime 3/ VIN = 12 V -55C to +125C 01 60 typical ns Driver ON resistance VIN = 4.5 V sink/source -55C to +125C 01 7.5 typical VIN = 12 V sink/source 5 typical Output power MOSFETs (PH pins) section Phase node voltage when disabled DC conditions and no load, ENA = 0 V -55C to +125C 01 0.5 typical V Volt
40、age drop, low side FET and diode VIN = 4.5 V, Idc = 100 mA -55C to +125C 01 1.42 V VIN = 12 V, Idc = 100 mA 1.38 High side power 4/ MOSFET switch rDS(ON)VIN = 4.5 V, BOOT-PH = 4.5 V, IO= 0.5 A -55C to +125C 01 300 m VIN = 12 V, BOOT-PH = 8 V, IO= 0.5 A 220 1/ Testing and other quality control techni
41、ques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performanc
42、e is assured by characterization and/or design. 2/ Unless otherwise specified, TJ= -55C to +125C and VI= 4.5 V to 20 V. 3/ Ensured by design, not production tested. 4/ Resistance from VIN to PH pins. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DE
43、FENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06610 REV A PAGE 9 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO
44、. 16236 DWG NO. V62/06610 REV A PAGE 10 Case X Symbol Dimensions Inches Millimeters Min Max Min Max A - .047 - 1.20 A1 .001 .005 0.05 0.15 b .007 .011 0.19 0.30 c .005 nominal 0.15 nominal D .192 .200 4.90 5.10 e .025 nominal 0.65 nominal E .169 .177 4.30 4.50 E1 .244 .259 6.20 6.60 L .019 .029 0.50
45、 0.75 n 16 NOTE: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 mm ( .005 inch) per side. 3. This package is designed to be soldered to a thermal pad o
46、n the board. Refer to technical brief, power pad thermally enhanced package, manufacturers literature number SLMA002 for information regarding recommended board layout. This document is available from the manufacturer. 4. Falls within JEDEC MO-153. FIGURE 1. Case outline Continued. Provided by IHSNo
47、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06610 REV A PAGE 11 Device type 01 Case outline X Terminal number Terminal symbol 1 VIN 2 VIN 3 UVLO 4 PWRGD 5 RT 6 SYNC 7 ENA 8 COMP 9 VSENSE 10 AGND 11 PGND 12 VBIAS 13 LSG 14 PH 15 PH 16 BOOT NOTE: If there is not a pin 1 indicator, turn device to enable reading the symbol from left to right. Pin 1 is at
