1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 REV PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11
2、 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC S
3、ILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/07649 08-04-22 REV PAGE 1 OF 60 AMSC N/A 5962-V047-08 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07649 REV PA
4、GE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of 0C to +90C (devices type 01, 04, 05 and 06), an extended operating temperature range of -55C to +105C (device type
5、02) and an extended operating temperature range of -40C to +105C (device type 03). 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineer
6、ing documentation: V62/07649 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Clock Rate Temperature Range Circuit function 01 SM320C6455-EP 1 GHz 0C to +90C Fixed point digital signal Processor 02 SM320C645
7、5-EP 1 GHz -55C to +105C Fixed point digital signal Processor 03 SM320C6455-EP 1 GHz -40C to +105C Fixed point digital signal Processor 04 SM320C6455-EP 720 MHz 0C to +90C Fixed point digital signal Processor 05 SM320C6455-EP 850 MHz 0C to +90C Fixed point digital signal Processor 06 SM320C6455-EP 1
8、.2 GHz 0C to +90C Fixed point digital signal Processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 697 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the d
9、evice manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. Provided by IHSNot for ResaleNo reproductio
10、n or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07649 REV PAGE 3 1.3 Absolute maximum ratings. 2/ Supply voltage ranges: (CVDD) -0.5 V to +1.5 V 3/ (DVDD33) -0.5 V to +4.2 V 3/ (DVDDR, DVDD18, AVDLL1, AVDLL
11、2) . -0.5 V to +2.5 V 3/ (DVDD15) -0.5 V to +2.5 V 3/ (DVDD12, DVDDRM, AVDDT, AVDDA) -0.5 V to +1.5 V 3/ (PLLV1, PLLV2) . -0.5 V to +2.5 V 3/ Input voltage ranges: (VI): 3.3 V pins (except PCI capable pins) . -0.5 V to DVDD33+ 0.5 V PCI capable pins -0.5 V to DVDD33+ 0.5 V RGMII pins . -0.5 V to +2.
12、5 V DDR2 memory controller pins -0.5 V to +2.5 V Output voltage ranges: 3.3 V pins (except PCI capable pins) . -0.5 V to DVDD33+ 0.5 V PCI capable pins -0.5 V to DVDD33+ 0.5 V RGMII pins . -0.5 V to +2.5 V DDR2 memory controller pins -0.5 V to +2.5 V Operating case temperature ranges, (TC): Device t
13、ype 01, 04, 05 and 06 0C to +90C Device type 02 -55C to +105C Device type 03 -40C to +105C Storage temperature range, (TSTG) . -65C to +150C 1.4 Recommended operating conditions. Supply voltage, core (CVDD): device type 01, 02, and 03 . +1.2125 V to +1.2875 V device type 04, 05, and 06 . +1.1640 V t
14、o +1.2360 V Supply voltage, core (DVDDRM)required only for rapid IO: device type 01, 02, and 03 . +1.2125 V to +1.2875 V device type 04, 05, and 06 +1.1640 V to +1.2360 V Supply voltage, core (DVDD12, AVDDA, AVDDT)required only for rapid IO: device type 01, 02, and 03 . +1.1875 V to +1.3125 V device
15、 type 04, 05 and 06 +1.14 V to +1.26 V Supply voltage, I/O (DVDD33) +3.14 V to +3.46 V Supply voltage, I/O (DVDD18) +1.71 V to +1.89 V Supply voltage, I/O (AVDLL1) . +1.71 V to +1.89 V Supply voltage, I/O (AVDLL2) . +1.71 V to +1.89 V Reference voltage (VREFSSTL) 0.49DVDD18V to 0.51DVDD18V Supply vo
16、ltage, I/O (DVDD15): 1.8 V operation . +1.71 V to +1.89 V 1.5 V operation . +1.43 V to +1.57 V Reference voltage, (VREFHSTL): 1.8 V operation . +0.855 V to +0.945 V 1.5 V operation . +0.713 V to +0.787 V Supply voltage, PLL (PLLV1, PLLV2) . +1.71 V to +1.89 V Supply ground, (VSS) 0 V 2/ Stresses bey
17、ond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maxim
18、um-rated conditions for extended periods may affect device reliability. 3/ All voltage values are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.
19、V62/07649 REV PAGE 4 1.4 Recommended operating conditions - Continued. High level input voltage, (VIH): 3.3 V pins (except PCI cable and I2C pins) +2.0 V minimum PCI cable pins . 0.5DVDD33to DVDD33+ 0.5 V 4/ I2C pins 0.7DVDD33V minimum RGMII pins . VREFHSTL+ 0.10 to DVDD15+ 0.30 V DDR2 memory contro
20、ller pins (DC) VREFSSTL + 0.125 to DVDD18+ 0.3 V Low level input voltage, (VIL) (except PCI) . +0.8 V 3.3 V pins (except PCI cable and I2C pins) +0.8 V maximum PCI cable pins . -0.5 V to 0.3DVDD33V 4/ I2C pins 0.3DVDD33V maximum RGMII pins . -0.3 V to VREFHSTL 0.1 V DDR2 memory controller pins (DC)
21、-0.8 V to VREFSSTL 0.125 V Maximum voltage during overshoot/undershoot (VOS) (PCI capable pins) -3.5 V to 7.1 V 5/ Operating case temperature (TC): Device type 01, 04, 05 and 06: . 0C to +90C Device type 02 -55C to +105C Device type 03 -40C to +105C Thermal resistance characteristics case X: C/W Air
22、 flow (m/s) 1 Junction to case, RJC1.45 N/A 2 Junction to board, RJB8.34 N/A 3 16.1 0.00 4 13.0 1.0 5 11.9 2.0 6 Junction to free air, RJA10.7 3.0 0.37 0.00 0.89 1.0 1.01 1.5 7 Junction to package top, PsiJT1.17 3.0 7.6 0.0 6.7 1.0 6.4 1.5 8 Junction to board PsiJB5.8 3.0 m/s = meter per second _ 4/
23、 These rated numbers are from the PCI local bus specification. See data from manufacturer for more information. 5/ PCI capable pins can withstand a maximum overshoot/undershoot for up to 11 ns as required by the PCI local bus specification. Provided by IHSNot for ResaleNo reproduction or networking
24、permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07649 REV PAGE 5 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electroni
25、c Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. P
26、in 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance charac
27、teristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal co
28、nnections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 Test load circuit for AC timing measurement. The test load circuit for AC timing measurements shall be as specified in figure 4. 3.5.5 Timing waveforms.
29、The timing waveforms shall be as shown in figures 5-57. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07649 REV PAGE 6 TABLE I. Electrical performance characteri
30、stics. 1/ Limits Test Symbol Test condition 2/ Device type: All Min Max Unit 3.3 V pins (except PCI capable and I2C pins) DVDD33= MIN, IOH= MAX 0.8DVDD33PCI capable pins 3/ IOH = -0.5 mA, DVDD33= 3.3 V 0.9DVDD33RGMII pins DVDD15 -0.4 High level output voltage DDR2 memory controller pins VOH1.4 V 3.3
31、 V pins (except PCI capable and I2C pins) DVDD33= MIN, IOL= MAX 0.22DVDD33PCI capable pins 3/ IOH = -0.5 mA, DVDD33= 3.3 V 0.1DVDD33I2C Pulled up to 3.3 V, 3 mA sink current 0.4 RGMII pins 0.4 Low level output voltage DDR2 memory controller pins VOLV VI= VSSto DVDD33, pins without internal pullup or
32、 pulldown resistor -1 1 VI= VSSto DVDD33, pins without internal pullup resistor 50 400 3.3 V pins (except PCI capable and I2C pins) VI= VSSto DVDD33, pins without internal pulldown resistor -400 -50 I2C pins 0.1DVDD33 VI 0.9DVDD33-10 10 PCI capable pins 5/ -1000 1000 A Input current DC RGMII pins II
33、4/ 0.4 V AECLKOUT, CLKR1/GP0, CLKX1/GP3, SYSCLK4/GP1, EMU18:0, CLKR0, CLKX0 -8 EMIF pins (except AECLKOUT), NMI, TOUT0L, TINP0L, TOUT1L, TINP1L, PCI_EN, EMAC-capable pins (except RGMII pins), RESETSTAT , McBSP-capable pins (except CLKR1/GP0, CLKX1/GP3, CLKR0, CLKX0) GP7:4, and TDO -4 PCI capable pin
34、s 3/ -0.5 RGMII pins -8 High level output current DC DDR2 memory controller pins IOH4 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.
35、 V62/07649 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Test condition 2/ Min Max Unit AECLKOUT, CLKR1/GP0, CLKX1/GP3, SYSCLK4/GP1, EMU18:0, CLKR0, CLKX0 8 EMIF pins (except AECLKOUT), NMI, TOUT0L, TINP0L, TOUT1L, TINP1L, PCI_EN, EMAC-capable pins (excep
36、t RGMII pins), RESETSTAT , McBSP-capable pins (except CLKR1/GP0, CLKX1/GP3, CLKR0, CLKX0) GP7:4, and TDO 5 PCI capable pins 3/ 1.5 RGMII pins 8 Low level output current DDR2 memory controller pins IOL-4 mA Off state output current DC 3.3 V pins IOZ6/ VO= DVDD33or 0 V -20 20 A CVDD= 1.25 V, CPU frequ
37、ency = 1200 MHz 1.79 TYP CVDD= 1.25 V, CPU frequency = 1000 MHz 1.57 TYP CVDD= 1.2 V, CPU frequency = 850 MHz 1.30 TYP Core supply power 7/ PCDDCVDD= 1.2 V, CPU frequency = 720 MHz 1.18 TYP DVDD33= 3.3 V, DVDD18= DVDDR= 1.8 V, PLLV1 = PLLV2 = AVDLL1= AVDLL2= 1.8 V, CPU frequency = 1200 MHz 0.54 TYP
38、DVDD33= 3.3 V, DVDD18= DVDDR= 1.8 V, PLLV1 = PLLV2 = AVDLL1= AVDLL2= 1.8 V, CPU frequency = 1000 MHz 0.54 TYP DVDD33= 3.3 V, DVDD18= DVDDR= 1.8 V, PLLV1 = PLLV2 = AVDLL1= AVDLL2= 1.8 V, CPU frequency = 850 MHz 0.53 TYP I/O supply power 7/ PDDDDVDD33= 3.3 V, DVDD18= DVDDR= 1.8 V, PLLV1 = PLLV2 = AVDL
39、L1= AVDLL2= 1.8 V, CPU frequency = 720 MHz 0.52 TYP W Input capacitance CI10 Output capacitance CO10 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO
40、. 16236 DWG NO. V62/07649 REV PAGE 8 TABLE I. Electrical performance characteristics - Continued. Limits No Test Symbol Test condition 2/ Device type: All Min Max Unit Timing requirements for power supply sequence 1 Setup time, DVDD33supply stable before CVDD12supply stable tsu(DVDD33-CVDD12)0.5 200
41、 2 Setup time, DVDD33supply stable before all other supplies stable tsu(DVDD33-ALLSUP)See figure 5 0 200 ms Timing requirements for external interrupts 8/ 1 Width of the NMI interrupt pulse low tw(NMIL)6P 2 Width of the NMI interrupt pulse low tw(NMIH)See figure 6 6P ns Timing requirements for Reset
42、 9/ 10/ 11/ 5 Pulse duration, POR low tw(POR)256D 12/ 6 Pulse duration, RESET low tw(RESET)24C 7 Setup time, boot mode and configuration pins valid before POR high or RESET high 13/ tsu(boot)6P 8 Hold time, boot mode and configuration pins valid before POR high or RESET high 13/ th(boot)See figure 7
43、and 8 6P ns Switching characteristics over recommended operating conditions during reset 9/ 9 Delay time, POR high and RESET high to RESETSTAT high See figure 7 15000C ns PLL1 AND PLL1 CONTROLLER PLL1 clock frequency ranges CLKIN1 66.6 PLLREF (PLLEN = 1) 18/ 33.3 66.6 PLLOUT 400 1200 SYSCLK4 25 166
44、SYSCLK5 333 MHz PLL1 stabilization, lock, and reset times 9/ PLL stabilization time 150 s PLL lock time 2000C ns PLL reset time 128C ns Timing requirements for CLKIN1 devices 17/ 1 Cycles time, CLKIN1 16/ tc(CLKIN1)15 30.3 2 Pulse duration, CLKIN1 high tw(CLKIN1H)0.4C 3 Pulse duration, CLKIN1 low tw
45、(CLKIN1L)4 Transition time, CLKIN1 tt(CLKIN1)1.2 ns 5 Period jitter (peak to peak), CLKIN1 tJ(CLKIN1)See figure 9 100 ps See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZ
46、E A CODE IDENT NO. 16236 DWG NO. V62/07649 REV PAGE 9 TABLE I. Electrical performance characteristics - Continued. Limits No Test Symbol Test condition 2/ Device type: All Min Max Unit PLL1 AND PLL1 CONTROLLER - Continued Switching characteristics over recommended operating conditions for SYSCLK4 CP
47、U/8 CPU/12 2 Pulse duration, SYSCLK4 high tw(CKO3H)4P-0.7 6P+0.7 3 Pulse duration, SYSCLK4 low tw(CKO3L)6P+04 Transition time, SYSCLK4 tt(CKO3)See figure 10 1 ns PLL2 AND PLL2 CONTROLLER PLL2 clock frequency ranges PLLREF (PLLEN = 1) 12.5 26.7 PLLOUT 250 533 SYSCLK1 19/ 50 125 MHz Timing requirement
48、s for CLKIN2 14/ 20/ 21/ 1 Cycles time, CLKIN2 tc(CLKIN2)37.5 80 2 Pulse duration, CLKIN2 high tw(CLKIN2H)0.4C 3 Pulse duration, CLKIN2 low tw(CLKIN2L)4 Transition time, CLKIN2 tt(CLKIN2)1.2 ns 5 Period jitter (peak to peak), CLKIN2 tJ(CLKIN2)See figure 11 100 ps EMIFA ELECTRICAL DATA/TIMING Timing requirements for ECLKIN for EMIFA 14/ 22/ 1 Cycle
